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authorAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:08 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:08 -0500
commita62afd094b75f52471ff2556c62c9c5f53d705e6 (patch)
treec7d7d1dbbfd29c7bba2ef11a124cef014f5dff0c /src/arch
parent08a5fd328b25d2ff431dc8f593c2d1bf3816b36e (diff)
downloadgem5-a62afd094b75f52471ff2556c62c9c5f53d705e6.tar.xz
scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/linux/system.hh3
-rw-r--r--src/arch/arm/isa/insts/neon.isa2
-rw-r--r--src/arch/x86/interrupts.cc2
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa5
4 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 345c17bb7..4f030c99f 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -89,10 +89,13 @@ class LinuxAlphaSystem : public AlphaSystem
/** Event to halt the simulator if the kernel calls panic() */
BreakPCEvent *kernelPanicEvent;
+#if 0
/** Event to halt the simulator if the kernel calls die_if_kernel */
BreakPCEvent *kernelDieEvent;
#endif
+#endif
+
/**
* Event to skip determine_cpu_caches() because we don't support
* the IPRs that the code can access to figure out cache sizes
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 3296b3b55..876bb3bb7 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2820,6 +2820,7 @@ let {{
4, vcvts2fpCode, fromInt = True)
vcvts2hCode = '''
+ destElem = 0;
FPSCR fpscr = (FPSCR) FpscrExc;
float srcFp1 = bitsToFp(srcElem1, (float)0.0);
if (flushToZero(srcFp1))
@@ -2836,6 +2837,7 @@ let {{
twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode)
vcvth2sCode = '''
+ destElem = 0;
FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(VfpRoundNearest);
__asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem)
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index c693e6bbd..9983d7305 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -627,7 +627,7 @@ X86ISA::Interrupts::Interrupts(Params * p) :
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
- intSlavePort(name() + ".int_slave", this, this, latency)
+ intSlavePort(name() + ".int_slave", this, this)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 040f5d04f..a6173831c 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -399,8 +399,9 @@
// Really only the LSB matters, but the decoder
// will sign extend it, and there's no easy way to
// specify only checking the first byte.
- -0x80: SyscallInst::int80('xc->syscall(Rax)',
- IsSyscall, IsNonSpeculative, IsSerializeAfter);
+ 0xffffffffffffff80:
+ SyscallInst::int80('xc->syscall(Rax)',
+ IsSyscall, IsNonSpeculative, IsSerializeAfter);
}
}
0x6: decode MODE_SUBMODE {