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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-04 20:22:56 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-04 20:22:56 -0500 |
commit | b0f11f8f81b114739b70502066b9ff5e9f556b7b (patch) | |
tree | fb4afbfa48e26e46b0954568aeccee196c69b621 /src/arch | |
parent | e6b4fed75d8b1044835bfbef77934b9a47bb2680 (diff) | |
parent | b46aa884354451fdf642ea836e3442d4179e73fb (diff) | |
download | gem5-b0f11f8f81b114739b70502066b9ff5e9f556b7b.tar.xz |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : e8ac13e1222796ab362fabb9b19694682538da29
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/sparc/miscregfile.cc | 6 | ||||
-rw-r--r-- | src/arch/sparc/ua2005.cc | 35 |
2 files changed, 28 insertions, 13 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 53559c072..68c6fa84a 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -321,9 +321,9 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) // I'm not sure why legion ignores the lowest two bits, but we'll go // with it // change from curCycle() to instCount() until we're done with legion - DPRINTFN("Instruction Count when TICK read: %#X stick=%#X\n", + DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", tc->getCpuPtr()->instCount(), stick); - return mbits(tc->getCpuPtr()->instCount() + (int32_t)stick,62,2) | + return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | mbits(tick,63,63); case MISCREG_FPRS: warn("FPRS register read and FPU stuff not really implemented\n"); @@ -615,7 +615,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, // use stick for offset and tick for holding intrrupt bit stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); tick = mbits(val,63,63); - DPRINTFN("Writing TICK=%#X\n", val); + DPRINTF(Timer, "Writing TICK=%#X\n", val); break; case MISCREG_FPRS: //Configure the fpu based on the fprs diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 0db5f6acc..66d699fce 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -64,19 +64,20 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, time = (tick_cmpr & mask(63)) - (tick & mask(63)); if (!(tick_cmpr & ~mask(63)) && time > 0) tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); - warn ("writing to TICK compare register %#X\n", val); + panic("writing to TICK compare register %#X\n", val); break; case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); setReg(miscReg, val); - if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) + if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) sTickCompare->deschedule(); - time = (stick_cmpr & mask(63)) - (stick & mask(63)); + time = ((int64_t)(stick_cmpr & mask(63)) + (int64_t)stick) - + tc->getCpuPtr()->instCount(); if (!(stick_cmpr & ~mask(63)) && time > 0) - sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); - warn ("writing to sTICK compare register value %#X\n", val); + sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); + DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); break; case MISCREG_PSTATE: @@ -116,11 +117,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); setReg(miscReg, val); - if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) + if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) hSTickCompare->deschedule(); - time = (hstick_cmpr & mask(63)) - (stick & mask(63)); + time = ((int64_t)(hstick_cmpr & mask(63)) + (int64_t)stick) - + tc->getCpuPtr()->instCount(); if (!(hstick_cmpr & ~mask(63)) && time > 0) - hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); warn ("writing to hsTICK compare register value %#X\n", val); break; @@ -191,12 +193,25 @@ MiscRegFile::processTickCompare(ThreadContext *tc) void MiscRegFile::processSTickCompare(ThreadContext *tc) { - panic("tick compare not implemented\n"); + // since our microcode instructions take two cycles we need to check if + // we're actually at the correct cycle or we need to wait a little while + // more + int ticks; + ticks = (stick_cmpr & mask(63)) - tc->getCpuPtr()->instCount(); + assert(ticks >= 0 && "stick compare missed interrupt cycle"); + + if (ticks == 0) { + DPRINTF(Timer, "STick compare cycle reached at %#x\n", + (stick_cmpr & mask(63))); + tc->getCpuPtr()->checkInterrupts = true; + + } else + sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); } void MiscRegFile::processHSTickCompare(ThreadContext *tc) { - panic("tick compare not implemented\n"); + panic("hstick compare not implemented\n"); } |