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| author | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-11-16 15:45:00 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-06-26 14:32:23 +0000 |
| commit | cb2be9940a055bf73647e9eef3779992d5af36b7 (patch) | |
| tree | f62d5288ee79db4debbef3ad7ee8964d833dd693 /src/arch | |
| parent | 0f50b6252bceb49547dfa05c3eba1a0e1e209d7d (diff) | |
| download | gem5-cb2be9940a055bf73647e9eef3779992d5af36b7.tar.xz | |
arch, arm: Update miscRegs in getTE
Normally, a translation will start via translateTiming/functional
which will check if the miscRegs have been updated and if so,
will update the TLB state accordingly. However, in a 2 stage
system, if there is a hit in stage 1, the resulting IPA will be
sent to the S2-TLB for translation via a getTE() function call
(via the stage2_lookup object). This will cause the state of the
S2-TLB to be out of sync.
Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/tlb.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f30e195c1..2b50d4b28 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1418,6 +1418,11 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) { + // In a 2-stage system, the IPA->PA translation can be started via this + // call so make sure the miscRegs are correct. + if (isStage2) { + updateMiscReg(tc, tranType); + } bool is_fetch = (mode == Execute); bool is_write = (mode == Write); |