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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-25 10:39:50 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-26 09:45:47 +0000 |
| commit | d4b3e064adeeace3c3e7d106801f95c14637c12f (patch) | |
| tree | 101e2d08102316a296fa75d8be0a26106da28e53 /src/arch | |
| parent | f5c8fc6bbedfe62bcb9514568b8ee13e073c807b (diff) | |
| download | gem5-d4b3e064adeeace3c3e7d106801f95c14637c12f.tar.xz | |
arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or
15) is implementation defined; this makes it trappable by having
HCR_EL2.TIDCP = 1.
Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13780
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 07123bd7d..ebe72dd52 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1228,6 +1228,11 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, break; } break; + case 11: + case 15: + // SYS Instruction with CRn = { 11, 15 } + // (Trappable by HCR_EL2.TIDCP) + return MISCREG_IMPDEF_UNIMPL; } break; case 2: |