style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

29 files changed, 68 insertions, 68 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index a114afaea..d6de363a7 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -349,7 +349,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 0; i < 8; ++i) {
                                  uint8_t ra_ub = Ra_uq<hi:lo>;
                                  uint8_t rb_ub = Rb_uq<hi:lo>;
-                                 temp += (ra_ub >= rb_ub) ? 
+                                 temp += (ra_ub >= rb_ub) ?
                                          (ra_ub - rb_ub) : (rb_ub - ra_ub);
                                  hi += 8;
                                  lo += 8;
@@ -378,15 +378,15 @@ decode OPCODE default Unknown::unknown() {
                              if (!(temp<7:0>)) { temp >>= 8; count += 8; }
                              if (!(temp<3:0>)) { temp >>= 4; count += 4; }
                              if (!(temp<1:0>)) { temp >>= 2; count += 2; }
-                             if (!(temp<0:0> & ULL(0x1))) { 
-                                 temp >>= 1; count += 1; 
+                             if (!(temp<0:0> & ULL(0x1))) {
+                                 temp >>= 1; count += 1;
                              }
                              if (!(temp<0:0> & ULL(0x1))) count += 1;
                              Rc = count;
                            }}, IntAluOp);
 
 
-            0x34: unpkbw({{ 
+            0x34: unpkbw({{
                              Rc = (Rb_uq<7:0>
                                    | (Rb_uq<15:8> << 16)
                                    | (Rb_uq<23:16> << 32)
@@ -415,7 +415,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 7; i >= 0; --i) {
                                  int8_t ra_sb = Ra_uq<hi:lo>;
                                  int8_t rb_sb = Rb_uq<hi:lo>;
-                                 temp = ((temp << 8) 
+                                 temp = ((temp << 8)
                                          | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 8;
@@ -431,7 +431,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 3; i >= 0; --i) {
                                  int16_t ra_sw = Ra_uq<hi:lo>;
                                  int16_t rb_sw = Rb_uq<hi:lo>;
-                                 temp = ((temp << 16) 
+                                 temp = ((temp << 16)
                                          | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 16;
@@ -447,7 +447,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 7; i >= 0; --i) {
                                  uint8_t ra_ub = Ra_uq<hi:lo>;
                                  uint8_t rb_ub = Rb_uq<hi:lo>;
-                                 temp = ((temp << 8) 
+                                 temp = ((temp << 8)
                                          | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 8;
@@ -463,7 +463,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 3; i >= 0; --i) {
                                  uint16_t ra_sw = Ra_uq<hi:lo>;
                                  uint16_t rb_sw = Rb_uq<hi:lo>;
-                                 temp = ((temp << 16) 
+                                 temp = ((temp << 16)
                                          | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 16;
@@ -479,7 +479,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 7; i >= 0; --i) {
                                  uint8_t ra_ub = Ra_uq<hi:lo>;
                                  uint8_t rb_ub = Rb_uq<hi:lo>;
-                                 temp = ((temp << 8) 
+                                 temp = ((temp << 8)
                                          | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 8;
@@ -495,7 +495,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 3; i >= 0; --i) {
                                  uint16_t ra_uw = Ra_uq<hi:lo>;
                                  uint16_t rb_uw = Rb_uq<hi:lo>;
-                                 temp = ((temp << 16) 
+                                 temp = ((temp << 16)
                                          | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 16;
@@ -511,7 +511,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 7; i >= 0; --i) {
                                  int8_t ra_sb = Ra_uq<hi:lo>;
                                  int8_t rb_sb = Rb_uq<hi:lo>;
-                                 temp = ((temp << 8) 
+                                 temp = ((temp << 8)
                                          | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 8;
@@ -527,7 +527,7 @@ decode OPCODE default Unknown::unknown() {
                              for (int i = 3; i >= 0; --i) {
                                  int16_t ra_sw = Ra_uq<hi:lo>;
                                  int16_t rb_sw = Rb_uq<hi:lo>;
-                                 temp = ((temp << 16) 
+                                 temp = ((temp << 16)
                                          | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
                                                           : Rb_uq<hi:lo>));
                                  hi -= 16;
diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh
index 115508405..f019b4f21 100644
--- a/src/arch/alpha/linux/linux.hh
+++ b/src/arch/alpha/linux/linux.hh
@@ -127,7 +127,7 @@ class AlphaLinux : public Linux
     static const unsigned TGT_RLIMIT_AS = 7;
     static const unsigned TGT_RLIMIT_NOFILE = 6;
     static const unsigned TGT_RLIMIT_MEMLOCK = 9;
-   
+
     typedef struct {
        int64_t  uptime;    /* Seconds since boot */
        uint64_t loads[3];  /* 1, 5, and 15 minute load averages */
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index e214c8874..3b37b42c7 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -75,7 +75,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
     ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
     if(elfObject)
     {
-        // modern glibc uses a bunch of auxiliary vectors to set up 
+        // modern glibc uses a bunch of auxiliary vectors to set up
         // TLS as well as do a bunch of other stuff
         // these vectors go on the bottom of the stack, below argc/argv/envp
         // pointers but above actual arg strings
@@ -111,10 +111,10 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
     }
 
     int space_needed =
-        argv_array_size + 
-        envp_array_size + 
+        argv_array_size +
+        envp_array_size +
         auxv_array_size +
-        arg_data_size + 
+        arg_data_size +
         env_data_size;
 
     if (space_needed < 32*1024)
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 5f0ed85db..3360b34c5 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -230,9 +230,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
             req->setPaddr(req->getPaddr() & PAddrUncachedMask);
         }
         // We shouldn't be able to read from an uncachable address in Alpha as
-        // we don't have a ROM and we don't want to try to fetch from a device 
-        // register as we destroy any data that is clear-on-read. 
-        if (req->isUncacheable() && itb) 
+        // we don't have a ROM and we don't want to try to fetch from a device
+        // register as we destroy any data that is clear-on-read.
+        if (req->isUncacheable() && itb)
             return std::make_shared<UnimpFault>(
                 "CPU trying to fetch from uncached I/O");
 
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index f6c8f3c44..1aab3dc1b 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -45,7 +45,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'arm':
 # Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308 
+# Scons bug id: 2006 M5 Bug id: 308
     Dir('isa/formats')
     Source('decoder.cc')
     Source('faults.cc')
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index 6682b75a0..4f57ecc51 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -39,7 +39,7 @@
 
 #include "arch/arm/interrupts.hh"
 #include "arch/arm/system.hh"
-    
+
 ArmISA::Interrupts *
 ArmInterruptsParams::create()
 {
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index fc4b97984..ba9a39efb 100644
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -65,7 +65,7 @@ def bitfield OPCODE_18     opcode18;
 def bitfield OPCODE_15_12  opcode15_12;
 def bitfield OPCODE_15     opcode15;
 def bitfield MISC_OPCODE   miscOpcode;
-def bitfield OPC2          opc2; 
+def bitfield OPC2          opc2;
 def bitfield OPCODE_7      opcode7;
 def bitfield OPCODE_6      opcode6;
 def bitfield OPCODE_4      opcode4;
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index b9745e8ba..8d254f571 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -41,7 +41,7 @@
 // Authors: Stephen Hines
 
 let {{
- 
+
      calcCcCode = '''
         if (%(canOverflow)s){
            cprintf("canOverflow: %%d\\n", Rd < resTemp);
@@ -52,7 +52,7 @@ let {{
             _iz = (resTemp == 0);
             _iv = %(ivValue)s;
             _ic = %(icValue)s;
-            
+
             CondCodesNZ =  (_in << 1) | (_iz);
             CondCodesC  =  _ic;
             CondCodesV  =  _iv;
@@ -79,7 +79,7 @@ let {{
             iv = 'CondCodesV'
             negBit = 63
         elif flagtype == "overflow":
-            canOverflow = "true" 
+            canOverflow = "true"
             icReg = icImm = iv = '0'
         elif flagtype == "add":
             icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
@@ -94,12 +94,12 @@ let {{
             icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
             icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
             iv = 'CondCodesV'
-        return (calcCcCode % {"icValue" : icReg, 
-                              "ivValue" : iv, 
+        return (calcCcCode % {"icValue" : icReg,
+                              "ivValue" : iv,
                               "negBit" : negBit,
                               "canOverflow" : canOverflow },
-               calcCcCode % {"icValue" : icImm, 
-                              "ivValue" : iv, 
+               calcCcCode % {"icValue" : icImm,
+                              "ivValue" : iv,
                               "negBit" : negBit,
                               "canOverflow" : canOverflow })
 
@@ -116,7 +116,7 @@ let {{
             negBit = 63
         elif flagtype == "overflow":
             icVaule = ivValue = '0'
-            canOverflow = "true" 
+            canOverflow = "true"
         elif flagtype == "add":
             icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
             ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index 0dd1df373..dd2f1675d 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -177,7 +177,7 @@ class ArmLinux32 : public Linux
         uint32_t freehigh;  /* Available high memory size */
         uint32_t mem_unit;  /* Memory unit size in bytes */
     } tgt_sysinfo;
-   
+
     /// For getrusage().
     struct rusage {
         struct timeval ru_utime;        //!< user time used
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index 7cc650c58..0246ffd4e 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -170,7 +170,7 @@ namespace ArmISA
     StackTrace::dump()
     {
         DPRINTFN("------ Stack ------\n");
-    
+
         DPRINTFN(" Not implemented\n");
     }
 #endif
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 52cbc4041..1f930f3f5 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -359,7 +359,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 Rt &= 0xFFFFE7FF;
                         }
                     }});
-                    0x4: mtc0({{ 
+                    0x4: mtc0({{
                         CP0_RD_SEL = Rt;
                         CauseReg cause = Cause;
                         IntCtlReg intCtl = IntCtl;
@@ -1238,7 +1238,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x3: CP1Unimpl::unknown();
                     0x7: CP1Unimpl::unknown();
 
-                    //Table A-16 MIPS32 COP1 Encoding of Function 
+                    //Table A-16 MIPS32 COP1 Encoding of Function
                     //Field When rs=W
                     0x4: decode FUNCTION {
                         format FloatConvertOp {
@@ -1867,7 +1867,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             }});
                             0x7: precr_sra_r_ph_w({{
                                 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
-                                                    SIMD_FMT_W, ROUND); 
+                                                    SIMD_FMT_W, ROUND);
                             }});
                         }
                     }
diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh
index 992bbf85d..38f958c89 100644
--- a/src/arch/mips/linux/linux.hh
+++ b/src/arch/mips/linux/linux.hh
@@ -125,7 +125,7 @@ class MipsLinux : public Linux
     /// assign themselves to process IDs reserved for
     /// the root users.
     static const int NUM_ROOT_PROCS = 2;
-   
+
     typedef struct {
        int32_t  uptime;    /* Seconds since boot */
        uint32_t loads[3];  /* 1, 5, and 15 minute load averages */
@@ -140,7 +140,7 @@ class MipsLinux : public Linux
        uint32_t freehigh;  /* Available high memory size */
        uint32_t mem_unit;  /* Memory unit size in bytes */
     } tgt_sysinfo;
-   
+
 };
 
 #endif
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index ef21179e5..c6c40188e 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -77,7 +77,7 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
 
     switch (op) {
       case 45:
-        { 
+        {
             // GSI_IEEE_FP_CONTROL
             TypedBufferArg<uint64_t> fpcr(bufPtr);
             // I don't think this exactly matches the HW FPCR
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cc4e4a859..cb129fba7 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -65,7 +65,7 @@ struct PTE
     bool V1;    // Odd entry Valid Bit
     uint8_t C1; // Cache Coherency Bits (3 bits)
 
-    /* 
+    /*
      * The next few variables are put in as optimizations to reduce
      * TLB lookup overheads. For a given Mask, what is the address shift
      * amount, and what is the OffsetMask
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index c49fab649..e26035cbe 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -32,7 +32,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'power':
 # Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308 
+# Scons bug id: 2006 M5 Bug id: 308
     Dir('isa/formats')
     Source('decoder.cc')
     Source('insts/branch.cc')
diff --git a/src/arch/sparc/interrupts.cc b/src/arch/sparc/interrupts.cc
index 96d61e559..1891361d5 100644
--- a/src/arch/sparc/interrupts.cc
+++ b/src/arch/sparc/interrupts.cc
@@ -29,7 +29,7 @@
  */
 
 #include "arch/sparc/interrupts.hh"
-    
+
 SparcISA::Interrupts *
 SparcInterruptsParams::create()
 {
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index bb7063edf..bbedc92b1 100644
--- a/src/arch/sparc/linux/linux.hh
+++ b/src/arch/sparc/linux/linux.hh
@@ -78,8 +78,8 @@ class SparcLinux : public Linux
 
     static const unsigned TGT_MAP_ANONYMOUS = 0x20;
     static const unsigned TGT_MAP_FIXED     = 0x10;
-   
-    typedef struct {   
+
+    typedef struct {
         int64_t  uptime;    /* Seconds since boot */
         uint64_t loads[3];  /* 1, 5, and 15 minute load averages */
         uint64_t totalram;  /* Total usable main memory size */
@@ -151,7 +151,7 @@ class Sparc32Linux : public SparcLinux
         uint32_t __unused4;
         uint32_t __unused5;
     } tgt_stat64;
-      
+
     typedef struct {
         int32_t  uptime;    /* Seconds since boot */
         uint32_t loads[3];  /* 1, 5, and 15 minute load averages */
@@ -165,7 +165,7 @@ class Sparc32Linux : public SparcLinux
         uint32_t totalhigh; /* Total high memory size */
         uint32_t freehigh;  /* Available high memory size */
         uint32_t mem_unit;  /* Memory unit size in bytes */
-    } tgt_sysinfo;   
+    } tgt_sysinfo;
 
     /// Resource constants for getrlimit() (overide some generics).
     static const unsigned TGT_RLIMIT_NPROC = 7;
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 79b4d3cc5..20df5a653 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -57,7 +57,7 @@ class TteTag
     TteTag(uint64_t e) : entry(e), populated(true) {}
 
     const TteTag &
-    operator=(uint64_t e) 
+    operator=(uint64_t e)
     {
         populated = true;
         entry = e;
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index e15dcd331..6817ca742 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -49,7 +49,7 @@ namespace X86ISA {
         L2L3CacheAndL2TLB,
         APMInfo,
         LongModeAddressSize,
- 
+
         /*
          * The following are defined by the spec but not yet implemented
          */
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index b7d9335d4..7724c0217 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -103,7 +103,7 @@ namespace X86ISA
 
         return ss.str();
     }
-    
+
     void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
     {
         X86FaultBase::invoke(tc);
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index cedd16820..1259b6982 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -68,7 +68,7 @@ namespace X86ISA
         {
             return ext & MediaScalarOp;
         }
-        
+
         int
         numItems(int size) const
         {
diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py
index d6f1a39bf..59519c0ae 100644
--- a/src/arch/x86/isa/insts/general_purpose/system_calls.py
+++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py
@@ -43,7 +43,7 @@ def macroop SYSCALL_64
 
     # Save the next RIP.
     rdip rcx
-    
+
     # Stick rflags with RF masked into r11.
     rflags t2
     limm t3, "~RFBit", dataSize=8
@@ -96,7 +96,7 @@ def macroop SYSCALL_COMPAT
 
     # Save the next RIP.
     rdip rcx
-    
+
     # Stick rflags with RF masked into r11.
     rflags t2
     limm t3, "~RFBit", dataSize=8
diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py
index 10653e1cc..ed43171bb 100644
--- a/src/arch/x86/isa/insts/romutil.py
+++ b/src/arch/x86/isa/insts/romutil.py
@@ -66,7 +66,7 @@ def rom
     wrdh t9, t4, t2, dataSize=8
 
 
-    # 
+    #
     # Figure out where the stack should be
     #
 
@@ -74,7 +74,7 @@ def rom
     rdsel t11, ss
 
     # Check if we're changing privelege level. At this point we can assume
-    # we're going to a DPL that's less than or equal to the CPL. 
+    # we're going to a DPL that's less than or equal to the CPL.
     rdattr t10, hs, dataSize=8
     andi t10, t10, 3, dataSize=8
     rdattr t5, cs, dataSize=8
@@ -139,7 +139,7 @@ def rom
     # Build up the interrupt stack frame
     #
 
-    
+
     # Write out the contents of memory
     %(errorCodeCode)s
     st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8
@@ -173,7 +173,7 @@ def rom
 
     # Put the results into rflags
     wrflags t6, t10
-    
+
     eret
 };
 '''
diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
index 027747b52..c3df35708 100644
--- a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
@@ -50,7 +50,7 @@ def macroop MOVD_MMX_P {
 };
 
 def macroop MOVD_R_MMX {
-    mov2int reg, mmxm, size=dsz 
+    mov2int reg, mmxm, size=dsz
 };
 
 def macroop MOVD_M_MMX {
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 5798ac4b0..dc36d0edb 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -51,7 +51,7 @@ let {{
 
 let {{
     class X86Microop(object):
- 
+
         generatorNameTemplate = "generate_%s_%d"
 
         generatorTemplate = '''
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index e5f04109f..cdb3b4899 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -214,7 +214,7 @@ let {{
             if ext is None:
                 self.ext = 0
             else:
-                self.ext = ext 
+                self.ext = ext
 
         def getAllocator(self, microFlags):
             className = self.className
@@ -926,7 +926,7 @@ let {{
                 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
                 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
                 uint64_t resBits = arg1Bits + arg2Bits;
-                
+
                 if (ext & 0x2) {
                     if (signedOp()) {
                         int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -963,7 +963,7 @@ let {{
                 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
                 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
                 uint64_t resBits = arg1Bits - arg2Bits;
-                
+
                 if (ext & 0x2) {
                     if (signedOp()) {
                         int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -1025,7 +1025,7 @@ let {{
 
                 if (ext & 0x4)
                     resBits += (ULL(1) << (destBits - 1));
-                
+
                 if (multHi())
                     resBits >>= destBits;
 
@@ -1050,7 +1050,7 @@ let {{
                 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
                 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
                 uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
-                
+
                 result = insertBits(result, hiIndex, loIndex, resBits);
             }
             FpDestReg_uqw = result;
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 15515ed12..ef0c4cb18 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -238,7 +238,7 @@ let {{
             global exec_output
 
             # Stick all the code together so it can be searched at once
-            allCode = "|".join((code, flag_code, cond_check, else_code, 
+            allCode = "|".join((code, flag_code, cond_check, else_code,
                                 cond_control_flag_init))
             allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
                                    cond_control_flag_init))
@@ -786,7 +786,7 @@ let {{
                 PredecfBit = PredecfBit & ~(ext & ECFBit);
 
                 //If some combination of the CF bits need to be set, set them.
-                if ((ext & (CFBit | ECFBit)) && 
+                if ((ext & (CFBit | ECFBit)) &&
                         shiftAmt <= dataSize * 8 &&
                         bits(SrcReg1, shiftAmt - 1)) {
                     PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -1018,7 +1018,7 @@ let {{
                 int msb = bits(DestReg, dataSize * 8 - 1);
                 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
                 //If some combination of the CF bits need to be set, set them.
-                if ((ext & (CFBit | ECFBit)) && 
+                if ((ext & (CFBit | ECFBit)) &&
                         (realShiftAmt == 0) ? origCFBit : CFBits) {
                     PredcfofBits = PredcfofBits | (ext & CFBit);
                     PredecfBit = PredecfBit | (ext & ECFBit);
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 5a00ce78c..0e3cff937 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -612,7 +612,7 @@ I386LiveProcess::initState()
 
     argsInit(sizeof(uint32_t), PageBytes);
 
-    /* 
+    /*
      * Set up a GDT for this process. The whole GDT wouldn't really be for
      * this process, but the only parts we care about are.
      */
diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 2fb051953..ab513d839 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -74,7 +74,7 @@ namespace X86ISA
       public:
         Addr gdtStart()
         { return _gdtStart; }
-        
+
         Addr gdtSize()
         { return _gdtSize; }