misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

35 files changed, 229 insertions, 194 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index a71a24cfb..0fa6782a8 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
     xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -99,7 +99,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index f77c45854..949c2e665 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -203,7 +203,7 @@ TLB::lookup(Addr vpn, uint8_t asn)
 }
 
 Fault
-TLB::checkCacheability(RequestPtr &req, bool itb)
+TLB::checkCacheability(const RequestPtr &req, bool itb)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -372,7 +372,7 @@ TLB::unserialize(CheckpointIn &cp)
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if (FullSystem && PcPAL(req->getPC()))
@@ -449,7 +449,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     mode_type mode =
         (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
@@ -599,7 +599,7 @@ TLB::index(bool advance)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (mode == Execute)
         return translateInst(req, tc);
@@ -608,7 +608,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -616,7 +616,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+                      Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 08166bc6e..e28f260ea 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -114,7 +114,7 @@ class TLB : public BaseTLB
         return unimplBits == 0 || unimplBits == VAddrUnImplMask;
     }
 
-    static Fault checkCacheability(RequestPtr &req, bool itb = false);
+    static Fault checkCacheability(const RequestPtr &req, bool itb = false);
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
@@ -137,17 +137,18 @@ class TLB : public BaseTLB
     }
 
   protected:
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
 
   public:
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req, ThreadContext *tc,
+            Mode mode) const override;
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a4e9c7975..aaf209e30 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1595,16 +1595,20 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
               // can't be an atomic translation because that causes problems
               // with unexpected atomic snoop requests.
               warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
-              Request req(0, val, 0, flags,  Request::funcMasterId,
-                          tc->pcState().pc(), tc->contextId());
+
+              auto req = std::make_shared<Request>(
+                  0, val, 0, flags,  Request::funcMasterId,
+                  tc->pcState().pc(), tc->contextId());
+
               fault = getDTBPtr(tc)->translateFunctional(
-                      &req, tc, mode, tranType);
+                      req, tc, mode, tranType);
+
               TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
               HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
 
               MiscReg newVal;
               if (fault == NoFault) {
-                  Addr paddr = req.getPaddr();
+                  Addr paddr = req->getPaddr();
                   if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
                      ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
                       newVal = (paddr & mask(39, 12)) |
@@ -1774,7 +1778,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_AT_S1E3R_Xt:
           case MISCREG_AT_S1E3W_Xt:
             {
-                RequestPtr req = new Request;
+                RequestPtr req = std::make_shared<Request>();
                 Request::Flags flags = 0;
                 BaseTLB::Mode mode = BaseTLB::Read;
                 TLB::ArmTranslationType tranType = TLB::NormalTran;
@@ -1893,7 +1897,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                             "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
                             val, fsr, newVal);
                 }
-                delete req;
                 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
                 return;
             }
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index d33978522..e57ccc9d5 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -91,7 +91,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
     xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -111,7 +111,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     if (req->isSwap())
         return true;
diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index 7e78a3193..e74ec9071 100644
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -57,7 +57,7 @@ Fault
 Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
 
 {
-    fault = stage2Tlb->getTE(&stage2Te, &req, tc, mode, this, timing,
+    fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
                                    functional, false, tranType);
     // Call finish if we're done already
     if ((fault != NoFault) || (stage2Te != NULL)) {
@@ -67,19 +67,19 @@ Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
         // entry is now in the TLB this should always hit the cache.
         if (fault == NoFault) {
             if (ELIs64(tc, EL2))
-                fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc);
+                fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc);
             else
-                fault = stage2Tlb->checkPermissions(stage2Te, &req, mode);
+                fault = stage2Tlb->checkPermissions(stage2Te, req, mode);
         }
 
-        mergeTe(&req, mode);
+        mergeTe(req, mode);
         *destTe = stage1Te;
     }
     return fault;
 }
 
 void
-Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
+Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
 {
     // Check again that we haven't got a fault
     if (fault == NoFault) {
@@ -176,7 +176,7 @@ Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
 }
 
 void
-Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
+Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req,
     ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = _fault;
diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh
index 870276b0a..8ce3a3a39 100644
--- a/src/arch/arm/stage2_lookup.hh
+++ b/src/arch/arm/stage2_lookup.hh
@@ -68,13 +68,13 @@ class Stage2LookUp : public BaseTLB::Translation
     bool                    functional;
     TLB::ArmTranslationType tranType;
     TlbEntry                *stage2Te;
-    Request                 req;
+    RequestPtr              req;
     Fault                   fault;
     bool                    complete;
     bool                    selfDelete;
 
   public:
-    Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, RequestPtr _req,
+    Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
         TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
         bool _functional, TLB::ArmTranslationType _tranType) :
         stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req),
@@ -82,13 +82,14 @@ class Stage2LookUp : public BaseTLB::Translation
         functional(_functional), tranType(_tranType), stage2Te(nullptr),
         fault(NoFault), complete(false), selfDelete(false)
     {
-        req.setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
-                    s1Req->getFlags(), s1Req->masterId(), 0);
+        req = std::make_shared<Request>();
+        req->setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
+                     s1Req->getFlags(), s1Req->masterId(), 0);
     }
 
     Fault getTe(ThreadContext *tc, TlbEntry *destTe);
 
-    void mergeTe(RequestPtr req, BaseTLB::Mode mode);
+    void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
 
     void setSelfDelete() { selfDelete = true; }
 
@@ -96,7 +97,7 @@ class Stage2LookUp : public BaseTLB::Translation
 
     void markDelayed() {}
 
-    void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
+    void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
                 BaseTLB::Mode mode);
 };
 
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index ba820e339..c6f3ba7c1 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -67,17 +67,17 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
     Fault fault;
 
     // translate to physical address using the second stage MMU
-    Request req = Request();
-    req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
+    auto req = std::make_shared<Request>();
+    req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
     if (isFunctional) {
-        fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
+        fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
     } else {
-        fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
+        fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
     }
 
     // Now do the access.
-    if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
-        Packet pkt = Packet(&req, MemCmd::ReadReq);
+    if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
+        Packet pkt = Packet(req, MemCmd::ReadReq);
         pkt.dataStatic(data);
         if (isFunctional) {
             port.sendFunctional(&pkt);
@@ -116,7 +116,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
 }
 
 void
-Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
+Stage2MMU::Stage2Translation::finish(const Fault &_fault,
+                                     const RequestPtr &req,
                                      ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = _fault;
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index b01b08153..8787089dc 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -70,12 +70,12 @@ class Stage2MMU : public SimObject
     class Stage2Translation : public BaseTLB::Translation
     {
       private:
-        uint8_t   *data;
-        int       numBytes;
-        Request   req;
-        Event     *event;
-        Stage2MMU &parent;
-        Addr      oVAddr;
+        uint8_t      *data;
+        int          numBytes;
+        RequestPtr   req;
+        Event        *event;
+        Stage2MMU    &parent;
+        Addr         oVAddr;
 
       public:
         Fault fault;
@@ -87,18 +87,18 @@ class Stage2MMU : public SimObject
         markDelayed() {}
 
         void
-        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
+        finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
                BaseTLB::Mode mode);
 
         void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
         {
             numBytes = size;
-            req.setVirt(0, vaddr, size, flags, masterId, 0);
+            req->setVirt(0, vaddr, size, flags, masterId, 0);
         }
 
         void translateTiming(ThreadContext *tc)
         {
-            parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read);
+            parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
         }
     };
 
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ba445878b..0668d802a 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -184,7 +184,7 @@ TableWalker::drainResume()
 }
 
 Fault
-TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
+TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
                   uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
                   TLB::Translation *_trans, bool _timing, bool _functional,
                   bool secure, TLB::ArmTranslationType tranType,
@@ -2021,13 +2021,14 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
                            currState->tc->getCpuPtr()->clockPeriod(), flags);
             (this->*doDescriptor)();
         } else {
-            RequestPtr req = new Request(descAddr, numBytes, flags, masterId);
+            RequestPtr req = std::make_shared<Request>(
+                descAddr, numBytes, flags, masterId);
+
             req->taskId(ContextSwitchTaskId::DMA);
             PacketPtr  pkt = new Packet(req, MemCmd::ReadReq);
             pkt->dataStatic(data);
             port->sendFunctional(pkt);
             (this->*doDescriptor)();
-            delete req;
             delete pkt;
         }
     }
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 1957bef0d..57e3aed06 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -894,7 +894,8 @@ class TableWalker : public MemObject
 
     void regStats() override;
 
-    Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
+    Fault walk(const RequestPtr &req, ThreadContext *tc,
+               uint16_t asid, uint8_t _vmid,
                bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
                bool timing, bool functional, bool secure,
                TLB::ArmTranslationType tranType, bool _stage2Req);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 192f01bce..d2153e779 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -133,7 +133,8 @@ TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     const Addr paddr = req->getPaddr();
 
@@ -561,7 +562,7 @@ TLB::regProbePoints()
 }
 
 Fault
-TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
                  Translation *translation, bool &delay, bool timing)
 {
     updateMiscReg(tc);
@@ -601,7 +602,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
 }
 
 Fault
-TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
+TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode)
 {
     // a data cache maintenance instruction that operates by MVA does
     // not generate a Data Abort exeception due to a Permission fault
@@ -779,7 +780,7 @@ TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
 
 
 Fault
-TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
+TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
                         ThreadContext *tc)
 {
     assert(aarch64);
@@ -989,7 +990,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
 }
 
 Fault
-TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
         Translation *translation, bool &delay, bool timing,
         TLB::ArmTranslationType tranType, bool functional)
 {
@@ -1158,7 +1159,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
     TLB::ArmTranslationType tranType)
 {
     updateMiscReg(tc, tranType);
@@ -1179,7 +1180,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
 }
 
 Fault
-TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode,
     TLB::ArmTranslationType tranType)
 {
     updateMiscReg(tc, tranType);
@@ -1200,7 +1201,7 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
     Translation *translation, Mode mode, TLB::ArmTranslationType tranType)
 {
     updateMiscReg(tc, tranType);
@@ -1217,7 +1218,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::translateComplete(RequestPtr req, ThreadContext *tc,
+TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode, TLB::ArmTranslationType tranType,
         bool callFromS2)
 {
@@ -1404,7 +1405,7 @@ TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type)
 }
 
 Fault
-TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
         Translation *translation, bool timing, bool functional,
         bool is_secure, TLB::ArmTranslationType tranType)
 {
@@ -1466,7 +1467,8 @@ TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
 }
 
 Fault
-TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
+TLB::getResultTe(TlbEntry **te, const RequestPtr &req,
+        ThreadContext *tc, Mode mode,
         Translation *translation, bool timing, bool functional,
         TlbEntry *mergeTe)
 {
@@ -1549,7 +1551,8 @@ TLB::setTestInterface(SimObject *_ti)
 }
 
 Fault
-TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain)
+TLB::testTranslation(const RequestPtr &req, Mode mode,
+                     TlbEntry::DomainType domain)
 {
     if (!test || !req->hasSize() || req->getSize() == 0 ||
         req->isCacheMaintenance()) {
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index b8ea99054..336b31b78 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -77,7 +77,7 @@ class TlbTestInterface
      * @param mode Access type
      * @param domain Domain type
      */
-    virtual Fault translationCheck(RequestPtr req, bool is_priv,
+    virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
                                    BaseTLB::Mode mode,
                                    TlbEntry::DomainType domain) = 0;
 
@@ -227,16 +227,18 @@ class TLB : public BaseTLB
 
     void insert(Addr vaddr, TlbEntry &pte);
 
-    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
+    Fault getTE(TlbEntry **te, const RequestPtr &req,
+                ThreadContext *tc, Mode mode,
                 Translation *translation, bool timing, bool functional,
                 bool is_secure, ArmTranslationType tranType);
 
-    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
-                      Mode mode, Translation *translation, bool timing,
+    Fault getResultTe(TlbEntry **te, const RequestPtr &req,
+                      ThreadContext *tc, Mode mode,
+                      Translation *translation, bool timing,
                       bool functional, TlbEntry *mergeTe);
 
-    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
-    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
+    Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
+    Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
                              ThreadContext *tc);
 
 
@@ -292,9 +294,13 @@ class TLB : public BaseTLB
      */
     void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el);
 
-    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
-    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
-            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
+    Fault trickBoxCheck(const RequestPtr &req, Mode mode,
+                        TlbEntry::DomainType domain);
+
+    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
+                            bool is_exec, bool is_write,
+                            TlbEntry::DomainType domain,
+                            LookupLevel lookup_level);
 
     void printTlb() const;
 
@@ -318,10 +324,11 @@ class TLB : public BaseTLB
      * Do a functional lookup on the TLB (for checker cpu) that
      * behaves like a normal lookup without modifying any page table state.
      */
-    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
-            ArmTranslationType tranType);
+    Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
+            Mode mode, ArmTranslationType tranType);
     Fault
-    translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) override
+    translateFunctional(const RequestPtr &req,
+                        ThreadContext *tc, Mode mode) override
     {
         return translateFunctional(req, tc, mode, NormalTran);
     }
@@ -340,33 +347,35 @@ class TLB : public BaseTLB
         return _attr;
     }
 
-    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
+    Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay,
             bool timing, ArmTranslationType tranType, bool functional = false);
-    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
+    Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
+    Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
             ArmTranslationType tranType);
     Fault
-    translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) override
+    translateAtomic(const RequestPtr &req,
+                    ThreadContext *tc, Mode mode) override
     {
         return translateAtomic(req, tc, mode, NormalTran);
     }
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode,
             ArmTranslationType tranType);
     void
-    translateTiming(RequestPtr req, ThreadContext *tc,
+    translateTiming(const RequestPtr &req, ThreadContext *tc,
                     Translation *translation, Mode mode) override
     {
         translateTiming(req, tc, translation, mode, NormalTran);
     }
-    Fault translateComplete(RequestPtr req, ThreadContext *tc,
+    Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode, ArmTranslationType tranType,
             bool callFromS2);
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
 
     void drainResume() override;
 
@@ -446,7 +455,7 @@ private:
     bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
 
   public: /* Testing */
-    Fault testTranslation(RequestPtr req, Mode mode,
+    Fault testTranslation(const RequestPtr &req, Mode mode,
                           TlbEntry::DomainType domain);
     Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
                    TlbEntry::DomainType domain,
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index ab19dd38a..68738cba2 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -764,6 +764,7 @@ TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
       parsingStarted(false), mismatch(false),
       mismatchOnPcOrOpcode(false), parent(_parent)
 {
+    memReq = std::make_shared<Request>();
 }
 
 void
@@ -1048,7 +1049,7 @@ bool
 TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
                                     unsigned flags)
 {
-    Request* req = &memReq;
+    const RequestPtr &req = memReq;
     TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
 
     req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
diff --git a/src/arch/arm/tracers/tarmac_parser.hh b/src/arch/arm/tracers/tarmac_parser.hh
index 7e6a780a0..6acdd627e 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -197,7 +197,7 @@ class TarmacParserRecord : public TarmacBaseRecord
     bool mismatchOnPcOrOpcode;
 
     /** Request for memory write checks. */
-    Request memReq;
+    RequestPtr memReq;
 
   protected:
     TarmacParser& parent;
diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 872867819..3a6731541 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -70,7 +70,7 @@ try_translate(ThreadContext *tc, Addr addr)
     Fault fault;
     // Set up a functional memory Request to pass to the TLB
     // to get it to translate the vaddr to a paddr
-    Request req(0, addr, 64, 0x40, -1, 0, 0);
+    auto req = std::make_shared<Request>(0, addr, 64, 0x40, -1, 0, 0);
     ArmISA::TLB *tlb;
 
     // Check the TLBs for a translation
@@ -81,14 +81,14 @@ try_translate(ThreadContext *tc, Addr addr)
     // Calling translateFunctional invokes a table-walk if required
     // so we should always succeed
     tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
-    fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
+    fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
     if (fault == NoFault)
-        return std::make_pair(true, req.getPaddr());
+        return std::make_pair(true, req->getPaddr());
 
     tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
-    fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
+    fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
     if (fault == NoFault)
-        return std::make_pair(true, req.getPaddr());
+        return std::make_pair(true, req->getPaddr());
 
     return std::make_pair(false, 0);
 }
diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index f6537995b..a7e517bb1 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -63,7 +63,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
 }
 
@@ -76,7 +76,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     return true;
 }
diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc
index 807f06dab..aebdd4bfe 100644
--- a/src/arch/generic/tlb.cc
+++ b/src/arch/generic/tlb.cc
@@ -37,7 +37,7 @@
 #include "sim/process.hh"
 
 Fault
-GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
+GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode)
 {
     if (FullSystem)
         panic("Generic translation shouldn't be used in full system mode.\n");
@@ -52,7 +52,7 @@ GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
 }
 
 void
-GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
+GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -60,7 +60,8 @@ GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+                             Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index e0becf727..89180341c 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -77,7 +77,7 @@ class BaseTLB : public SimObject
          * be responsible for cleaning itself up which will happen in this
          * function. Once it's called, the object is no longer valid.
          */
-        virtual void finish(const Fault &fault, RequestPtr req,
+        virtual void finish(const Fault &fault, const RequestPtr &req,
                             ThreadContext *tc, Mode mode) = 0;
 
         /** This function is used by the page table walker to determine if it
@@ -92,12 +92,12 @@ class BaseTLB : public SimObject
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 
     virtual Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) = 0;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
     virtual void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) = 0;
     virtual Fault
-    translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+    translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
     {
         panic("Not implemented.\n");
     }
@@ -117,7 +117,7 @@ class BaseTLB : public SimObject
      * @return A fault on failure, NoFault otherwise.
      */
     virtual Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const = 0;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
 
     /**
      * Remove all entries from the TLB
@@ -154,13 +154,13 @@ class GenericTLB : public BaseTLB
     void demapPage(Addr vaddr, uint64_t asn) override;
 
     Fault translateAtomic(
-        RequestPtr req, ThreadContext *tc, Mode mode) override;
+        const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-        RequestPtr req, ThreadContext *tc,
+        const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode) override;
 
     Fault finalizePhysical(
-        RequestPtr req, ThreadContext *tc, Mode mode) const override;
+        const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
 };
 
 #endif // __ARCH_GENERIC_TLB_HH__
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 68a61feea..f1cec5ec1 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -461,7 +461,7 @@ namespace HsailISA
                             *d = gpuDynInst->wavefront()->ldsChunk->
                                 read<c0>(vaddr);
                         } else {
-                            RequestPtr req = new Request(0,
+                            RequestPtr req = std::make_shared<Request>(0,
                                 vaddr, sizeof(c0), 0,
                                 gpuDynInst->computeUnit()->masterId(),
                                 0, gpuDynInst->wfDynId);
@@ -589,7 +589,7 @@ namespace HsailISA
                     gpuDynInst->statusBitVector = VectorMask(1);
                     gpuDynInst->useContinuation = false;
                     // create request
-                    RequestPtr req = new Request(0, 0, 0, 0,
+                    RequestPtr req = std::make_shared<Request>(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
                                   0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
@@ -1015,7 +1015,7 @@ namespace HsailISA
                     gpuDynInst->execContinuation = &GPUStaticInst::execSt;
                     gpuDynInst->useContinuation = true;
                     // create request
-                    RequestPtr req = new Request(0, 0, 0, 0,
+                    RequestPtr req = std::make_shared<Request>(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
                                   0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
@@ -1066,10 +1066,10 @@ namespace HsailISA
                             gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr,
                                                                          *d);
                         } else {
-                            RequestPtr req =
-                              new Request(0, vaddr, sizeof(c0), 0,
-                                          gpuDynInst->computeUnit()->masterId(),
-                                          0, gpuDynInst->wfDynId);
+                            RequestPtr req = std::make_shared<Request>(
+                                0, vaddr, sizeof(c0), 0,
+                                gpuDynInst->computeUnit()->masterId(),
+                                0, gpuDynInst->wfDynId);
 
                             gpuDynInst->setRequestFlags(req);
                             PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
@@ -1489,7 +1489,7 @@ namespace HsailISA
                     gpuDynInst->useContinuation = true;
 
                     // create request
-                    RequestPtr req = new Request(0, 0, 0, 0,
+                    RequestPtr req = std::make_shared<Request>(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
                                   0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
@@ -1622,7 +1622,7 @@ namespace HsailISA
                         }
                     } else {
                         RequestPtr req =
-                            new Request(0, vaddr, sizeof(c0), 0,
+                            std::make_shared<Request>(0, vaddr, sizeof(c0), 0,
                                         gpuDynInst->computeUnit()->masterId(),
                                         0, gpuDynInst->wfDynId,
                                         gpuDynInst->makeAtomicOpFunctor<c0>(e,
@@ -1676,7 +1676,7 @@ namespace HsailISA
                     // the acquire completes
                     gpuDynInst->useContinuation = false;
                     // create request
-                    RequestPtr req = new Request(0, 0, 0, 0,
+                    RequestPtr req = std::make_shared<Request>(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
                                   0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 7fa1642a8..05d637ba7 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -75,7 +75,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
     xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
     xc->setMiscReg(MISCREG_LLFLAG, true);
@@ -92,7 +92,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index a18149dfa..46e250b2b 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -142,7 +142,7 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
 }
 
 inline Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(const RequestPtr &req)
 {
     Addr VAddrUncacheable = 0xA0000000;
     // In MIPS, cacheability is controlled by certain bits of the virtual
@@ -282,7 +282,7 @@ TLB::regStats()
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     if (FullSystem)
         panic("translateInst not implemented in MIPS.\n");
@@ -297,7 +297,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     if (FullSystem)
         panic("translateData not implemented in MIPS.\n");
@@ -312,7 +312,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (mode == Execute)
         return translateInst(req, tc);
@@ -321,7 +321,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -329,7 +329,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 626812af8..3a39747c0 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -104,7 +104,7 @@ class TLB : public BaseTLB
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);
 
-    static Fault checkCacheability(RequestPtr &req);
+    static Fault checkCacheability(const RequestPtr &req);
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
@@ -113,16 +113,17 @@ class TLB : public BaseTLB
     void regStats() override;
 
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
 
   private:
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
 };
 
 }
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index ff2f94fb6..703b92e2b 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -145,7 +145,7 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const
 }
 
 inline Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(const RequestPtr &req)
 {
     Addr VAddrUncacheable = 0xA0000000;
     if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
@@ -279,7 +279,7 @@ TLB::regStats()
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     // Instruction accesses must be word-aligned
     if (req->getVaddr() & 0x3) {
@@ -298,7 +298,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     Process * p = tc->getProcessPtr();
 
@@ -310,7 +310,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (FullSystem)
         fatal("translate atomic not yet implemented in full system mode.\n");
@@ -322,7 +322,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
                      Translation *translation, Mode mode)
 {
     assert(translation);
@@ -330,7 +330,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index ca82d0b45..0c5eeb1bd 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -159,16 +159,17 @@ class TLB : public BaseTLB
 
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);
-    static Fault checkCacheability(RequestPtr &req);
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    static Fault checkCacheability(const RequestPtr &req);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index 1583258a8..b1cde34c6 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -82,7 +82,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 
 template <class XC> inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
     locked_addrs.push(req->getPaddr() & ~0xF);
     DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
@@ -94,7 +94,7 @@ handleLockedSnoopHit(XC *xc)
 {}
 
 template <class XC> inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     // Normally RISC-V uses zero to indicate success and nonzero to indicate
     // failure (right now only 1 is reserved), but in gem5 zero indicates
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 0c5962ece..ffb135c5a 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -143,7 +143,7 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
 }
 
 inline Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(const RequestPtr &req)
 {
     Addr VAddrUncacheable = 0xA0000000;
     // In MIPS, cacheability is controlled by certain bits of the virtual
@@ -283,7 +283,7 @@ TLB::regStats()
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     if (FullSystem)
         panic("translateInst not implemented in RISC-V.\n");
@@ -298,7 +298,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     if (FullSystem)
         panic("translateData not implemented in RISC-V.\n");
@@ -324,7 +324,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (mode == Execute)
         return translateInst(req, tc);
@@ -333,7 +333,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -341,7 +341,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index ce63fd33a..5d6c9dfc0 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -103,7 +103,7 @@ class TLB : public BaseTLB
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);
 
-    static Fault checkCacheability(RequestPtr &req);
+    static Fault checkCacheability(const RequestPtr &req);
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
@@ -112,16 +112,17 @@ class TLB : public BaseTLB
     void regStats() override;
 
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
 
   private:
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
 };
 
 }
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 49b353a7c..328810a46 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -415,7 +415,7 @@ TLB::writeSfsr(Addr a, bool write, ContextType ct,
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
@@ -529,7 +529,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     /*
      * @todo this could really use some profiling and fixing to make
@@ -833,7 +833,7 @@ handleMmuRegAccess:
 };
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (mode == Execute)
         return translateInst(req, tc);
@@ -842,7 +842,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -850,7 +850,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 7437ec3e6..e5e6753be 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -146,8 +146,8 @@ class TLB : public BaseTLB
 
     void writeTagAccess(Addr va, int context);
 
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
 
   public:
     typedef SparcTLBParams Params;
@@ -164,12 +164,13 @@ class TLB : public BaseTLB
     void dumpAll();
 
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
     Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 6bf180432..83d80bb94 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -79,9 +79,11 @@ namespace X86ISA
     static inline PacketPtr
     prepIntRequest(const uint8_t id, Addr offset, Addr size)
     {
-        RequestPtr req = new Request(x86InterruptAddress(id, offset),
-                                     size, Request::UNCACHEABLE,
-                                     Request::intMasterId);
+        RequestPtr req = std::make_shared<Request>(
+            x86InterruptAddress(id, offset),
+            size, Request::UNCACHEABLE,
+            Request::intMasterId);
+
         PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
         pkt->allocate();
         return pkt;
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 998ea856a..11ec12245 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -68,7 +68,7 @@ namespace X86ISA {
 
 Fault
 Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
-              RequestPtr _req, BaseTLB::Mode _mode)
+              const RequestPtr &_req, BaseTLB::Mode _mode)
 {
     // TODO: in timing mode, instead of blocking when there are other
     // outstanding requests, see if this request can be coalesced with
@@ -514,8 +514,8 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
         //If we didn't return, we're setting up another read.
         Request::Flags flags = oldRead->req->getFlags();
         flags.set(Request::UNCACHEABLE, uncacheable);
-        RequestPtr request =
-            new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
+        RequestPtr request = std::make_shared<Request>(
+            nextRead, oldRead->getSize(), flags, walker->masterId);
         read = new Packet(request, MemCmd::ReadReq);
         read->allocate();
         // If we need to write, adjust the read packet to write the modified
@@ -526,7 +526,6 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
             write->cmd = MemCmd::WriteReq;
         } else {
             write = NULL;
-            delete oldRead->req;
             delete oldRead;
         }
     }
@@ -537,7 +536,6 @@ void
 Walker::WalkerState::endWalk()
 {
     nextState = Ready;
-    delete read->req;
     delete read;
     read = NULL;
 }
@@ -584,8 +582,10 @@ Walker::WalkerState::setupWalk(Addr vaddr)
     Request::Flags flags = Request::PHYSICAL;
     if (cr3.pcd)
         flags.set(Request::UNCACHEABLE);
-    RequestPtr request = new Request(topAddr, dataSize, flags,
-                                     walker->masterId);
+
+    RequestPtr request = std::make_shared<Request>(
+        topAddr, dataSize, flags, walker->masterId);
+
     read = new Packet(request, MemCmd::ReadReq);
     read->allocate();
 }
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index d5aa631d2..edca24795 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -113,12 +113,12 @@ namespace X86ISA
             bool started;
           public:
             WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
-                    RequestPtr _req, bool _isFunctional = false) :
-                        walker(_walker), req(_req), state(Ready),
-                        nextState(Ready), inflight(0),
-                        translation(_translation),
-                        functional(_isFunctional), timing(false),
-                        retrying(false), started(false)
+                        const RequestPtr &_req, bool _isFunctional = false) :
+                walker(_walker), req(_req), state(Ready),
+                nextState(Ready), inflight(0),
+                translation(_translation),
+                functional(_isFunctional), timing(false),
+                retrying(false), started(false)
             {
             }
             void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
@@ -157,7 +157,7 @@ namespace X86ISA
       public:
         // Kick off the state machine.
         Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
-                RequestPtr req, BaseTLB::Mode mode);
+                const RequestPtr &req, BaseTLB::Mode mode);
         Fault startFunctional(ThreadContext * _tc, Addr &addr,
                 unsigned &logBytes, BaseTLB::Mode mode);
         BaseMasterPort &getMasterPort(const std::string &if_name,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index a3aec1676..8e83208f4 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -170,7 +170,7 @@ TLB::demapPage(Addr va, uint64_t asn)
 }
 
 Fault
-TLB::translateInt(RequestPtr req, ThreadContext *tc)
+TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
 {
     DPRINTF(TLB, "Addresses references internal memory.\n");
     Addr vaddr = req->getVaddr();
@@ -224,7 +224,8 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+                      ThreadContext *tc, Mode mode) const
 {
     Addr paddr = req->getPaddr();
 
@@ -265,7 +266,8 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 }
 
 Fault
-TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
+TLB::translate(const RequestPtr &req,
+        ThreadContext *tc, Translation *translation,
         Mode mode, bool &delayedResponse, bool timing)
 {
     Request::Flags flags = req->getFlags();
@@ -425,14 +427,14 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     bool delayedResponse;
     return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     bool delayedResponse;
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 08804a455..827ab8166 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -106,9 +106,9 @@ namespace X86ISA
         Stats::Scalar rdMisses;
         Stats::Scalar wrMisses;
 
-        Fault translateInt(RequestPtr req, ThreadContext *tc);
+        Fault translateInt(const RequestPtr &req, ThreadContext *tc);
 
-        Fault translate(RequestPtr req, ThreadContext *tc,
+        Fault translate(const RequestPtr &req, ThreadContext *tc,
                 Translation *translation, Mode mode,
                 bool &delayedResponse, bool timing);
 
@@ -123,9 +123,9 @@ namespace X86ISA
         }
 
         Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
         void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
 
         /**
@@ -141,7 +141,7 @@ namespace X86ISA
          * @param mode Request type (read/write/execute).
          * @return A fault on failure, NoFault otherwise.
          */
-        Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
+        Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
                                Mode mode) const override;
 
         TlbEntry *insert(Addr vpn, const TlbEntry &entry);