Merge zizzer.eecs.umich.edu:/bk/newmem

into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/newmem-o3-micro

--HG--
extra : convert_revision : 3fa3fa4544ff8c9d2135e1befe6c8f4757006a2a

4 files changed, 9 insertions, 7 deletions

diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 3ef204850..4f27c72f5 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -103,7 +103,6 @@ output header {{
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
-#include "mem/request.hh"  // some constructors use MemReq flags
 #include "sim/faults.hh"
 }};
 
diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py
index 1372f7dba..530162bfd 100644
--- a/src/arch/x86/isa/insts/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/control_transfer/call.py
@@ -61,8 +61,8 @@ def macroop CALL_I
 
     limm t2, imm
     rdip t1
-    subi "INTREG_RSP", "INTREG_RSP", dsz
-    st t1, ss, [0, t0, "INTREG_RSP"]
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
     wrip t1, t2
 };
 '''
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index ca2443752..585437b8c 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -58,16 +58,16 @@ def macroop POP_R {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
 
-    ld reg, ss, [0, t0, "INTREG_RSP"]
-    addi "INTREG_RSP", "INTREG_RSP", dsz
+    ld reg, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
 };
 
 def macroop PUSH_R {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
 
-    subi "INTREG_RSP", "INTREG_RSP", dsz
-    st reg, ss, [0, t0, "INTREG_RSP"]
+    subi rsp, rsp, dsz
+    st reg, ss, [0, t0, rsp]
 };
 '''
 #let {{
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 4e06f4391..ee2b92f53 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -91,6 +91,9 @@ let {{
         "osz" : "env.operandSize",
         "ssz" : "env.stackSize"
     }
+
+    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
+        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
     assembler.symbols.update(symbols)
 
     # Code literal which forces a default 64 bit operand size in 64 bit mode.