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| author | Korey Sewell <ksewell@umich.edu> | 2007-06-22 21:09:35 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-06-22 21:09:35 -0400 |
| commit | ac19e0c5050219cbb0579a319fa3fab5cf92835d (patch) | |
| tree | 31d0755577a6553fa72246fba1dd664afa866ce6 /src/arch | |
| parent | c6d137f5655dec978e1555e17e3a850f88a541c4 (diff) | |
| download | gem5-ac19e0c5050219cbb0579a319fa3fab5cf92835d.tar.xz | |
FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...
src/arch/isa_parser.py:
add back deleted writeback in Control Operand
--HG--
extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db
Diffstat (limited to 'src/arch')
| -rwxr-xr-x | src/arch/isa_parser.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 95c57af2f..754a64fdb 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt -# Gabe Black # Korey Sewell import os @@ -1411,6 +1410,9 @@ class ControlRegOperand(Operand): error(0, 'Attempt to write control register as FP') wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + self.base_name + return wb class ControlBitfieldOperand(ControlRegOperand): def makeRead(self): |