tlb: Don't separate the TLB classes into an instruction TLB and a data TLB

14 files changed, 244 insertions, 532 deletions

diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 099327470..cdee54d26 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -33,15 +33,5 @@ from BaseTLB import BaseTLB
 
 class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class AlphaDTB(AlphaTLB):
-    type = 'AlphaDTB'
-    cxx_class = 'AlphaISA::DTB'
-    size = 64
-
-class AlphaITB(AlphaTLB):
-    type = 'AlphaITB'
-    cxx_class = 'AlphaISA::ITB'
-    size = 48
+    cxx_class = 'AlphaISA::TLB'
+    size = Param.Int(64, "TLB size")
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 2b0afacfe..d20a0adc2 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -72,6 +72,90 @@ TLB::~TLB()
         delete [] table;
 }
 
+void
+TLB::regStats()
+{
+    fetch_hits
+        .name(name() + ".fetch_hits")
+        .desc("ITB hits");
+    fetch_misses
+        .name(name() + ".fetch_misses")
+        .desc("ITB misses");
+    fetch_acv
+        .name(name() + ".fetch_acv")
+        .desc("ITB acv");
+    fetch_accesses
+        .name(name() + ".fetch_accesses")
+        .desc("ITB accesses");
+
+    fetch_accesses = fetch_hits + fetch_misses;
+
+    read_hits
+        .name(name() + ".read_hits")
+        .desc("DTB read hits")
+        ;
+
+    read_misses
+        .name(name() + ".read_misses")
+        .desc("DTB read misses")
+        ;
+
+    read_acv
+        .name(name() + ".read_acv")
+        .desc("DTB read access violations")
+        ;
+
+    read_accesses
+        .name(name() + ".read_accesses")
+        .desc("DTB read accesses")
+        ;
+
+    write_hits
+        .name(name() + ".write_hits")
+        .desc("DTB write hits")
+        ;
+
+    write_misses
+        .name(name() + ".write_misses")
+        .desc("DTB write misses")
+        ;
+
+    write_acv
+        .name(name() + ".write_acv")
+        .desc("DTB write access violations")
+        ;
+
+    write_accesses
+        .name(name() + ".write_accesses")
+        .desc("DTB write accesses")
+        ;
+
+    data_hits
+        .name(name() + ".data_hits")
+        .desc("DTB hits")
+        ;
+
+    data_misses
+        .name(name() + ".data_misses")
+        .desc("DTB misses")
+        ;
+
+    data_acv
+        .name(name() + ".data_acv")
+        .desc("DTB access violations")
+        ;
+
+    data_accesses
+        .name(name() + ".data_accesses")
+        .desc("DTB accesses")
+        ;
+
+    data_hits = read_hits + write_hits;
+    data_misses = read_misses + write_misses;
+    data_acv = read_acv + write_acv;
+    data_accesses = read_accesses + write_accesses;
+}
+
 // look up an entry in the TLB
 TlbEntry *
 TLB::lookup(Addr vpn, uint8_t asn)
@@ -288,36 +372,8 @@ TLB::unserialize(Checkpoint *cp, const string &section)
     }
 }
 
-///////////////////////////////////////////////////////////////////////
-//
-//  Alpha ITB
-//
-ITB::ITB(const Params *p)
-    : TLB(p)
-{}
-
-
-void
-ITB::regStats()
-{
-    hits
-        .name(name() + ".hits")
-        .desc("ITB hits");
-    misses
-        .name(name() + ".misses")
-        .desc("ITB misses");
-    acv
-        .name(name() + ".acv")
-        .desc("ITB acv");
-    accesses
-        .name(name() + ".accesses")
-        .desc("ITB accesses");
-
-    accesses = hits + misses;
-}
-
 Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -326,7 +382,7 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
     if (PcPAL(req->getPC())) {
         // strip off PAL PC marker (lsb is 1)
         req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
-        hits++;
+        fetch_hits++;
         return NoFault;
     }
 
@@ -335,7 +391,7 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
     } else {
         // verify that this is a good virtual address
         if (!validVirtualAddress(req->getVaddr())) {
-            acv++;
+            fetch_acv++;
             return new ItbAcvFault(req->getVaddr());
         }
 
@@ -352,7 +408,7 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
             // only valid in kernel mode
             if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
                 mode_kernel) {
-                acv++;
+                fetch_acv++;
                 return new ItbAcvFault(req->getVaddr());
             }
 
@@ -373,7 +429,7 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
                               asn);
 
             if (!entry) {
-                misses++;
+                fetch_misses++;
                 return new ItbPageFault(req->getVaddr());
             }
 
@@ -385,11 +441,11 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
             if (!(entry->xre &
                   (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
                 // instruction access fault
-                acv++;
+                fetch_acv++;
                 return new ItbAcvFault(req->getVaddr());
             }
 
-            hits++;
+            fetch_hits++;
         }
     }
 
@@ -401,93 +457,8 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 
 }
 
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc), req, tc, false);
-}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Alpha DTB
-//
-DTB::DTB(const Params *p)
-     : TLB(p)
-{}
-
-void
-DTB::regStats()
-{
-    read_hits
-        .name(name() + ".read_hits")
-        .desc("DTB read hits")
-        ;
-
-    read_misses
-        .name(name() + ".read_misses")
-        .desc("DTB read misses")
-        ;
-
-    read_acv
-        .name(name() + ".read_acv")
-        .desc("DTB read access violations")
-        ;
-
-    read_accesses
-        .name(name() + ".read_accesses")
-        .desc("DTB read accesses")
-        ;
-
-    write_hits
-        .name(name() + ".write_hits")
-        .desc("DTB write hits")
-        ;
-
-    write_misses
-        .name(name() + ".write_misses")
-        .desc("DTB write misses")
-        ;
-
-    write_acv
-        .name(name() + ".write_acv")
-        .desc("DTB write access violations")
-        ;
-
-    write_accesses
-        .name(name() + ".write_accesses")
-        .desc("DTB write accesses")
-        ;
-
-    hits
-        .name(name() + ".hits")
-        .desc("DTB hits")
-        ;
-
-    misses
-        .name(name() + ".misses")
-        .desc("DTB misses")
-        ;
-
-    acv
-        .name(name() + ".acv")
-        .desc("DTB access violations")
-        ;
-
-    accesses
-        .name(name() + ".accesses")
-        .desc("DTB accesses")
-        ;
-
-    hits = read_hits + write_hits;
-    misses = read_misses + write_misses;
-    acv = read_acv + write_acv;
-    accesses = read_accesses + write_accesses;
-}
-
 Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
     Addr pc = tc->readPC();
 
@@ -624,14 +595,6 @@ DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
     return checkCacheability(req);
 }
 
-void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc, write), req, tc, write);
-}
-
 TlbEntry &
 TLB::index(bool advance)
 {
@@ -643,16 +606,30 @@ TLB::index(bool advance)
     return *entry;
 }
 
-/* end namespace AlphaISA */ }
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+        bool write, bool execute)
+{
+    if (execute)
+        return translateInst(req, tc);
+    else
+        return translateData(req, tc, write);
+}
 
-AlphaISA::ITB *
-AlphaITBParams::create()
+void
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation,
+        bool write, bool execute)
 {
-    return new AlphaISA::ITB(this);
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write, execute),
+            req, tc, write, execute);
 }
 
-AlphaISA::DTB *
-AlphaDTBParams::create()
+/* end namespace AlphaISA */ }
+
+AlphaISA::TLB *
+AlphaTLBParams::create()
 {
-    return new AlphaISA::DTB(this);
+    return new AlphaISA::TLB(this);
 }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 643889534..292ba15f4 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -41,8 +41,7 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/AlphaDTB.hh"
-#include "params/AlphaITB.hh"
+#include "params/AlphaTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 
@@ -55,6 +54,24 @@ class TlbEntry;
 class TLB : public BaseTLB
 {
   protected:
+    mutable Stats::Scalar fetch_hits;
+    mutable Stats::Scalar fetch_misses;
+    mutable Stats::Scalar fetch_acv;
+    mutable Stats::Formula fetch_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
+    Stats::Formula data_hits;
+    Stats::Formula data_misses;
+    Stats::Formula data_acv;
+    Stats::Formula data_accesses;
+
+
     typedef std::multimap<Addr, int> PageTable;
     PageTable lookupTable;  // Quick lookup into page table
 
@@ -70,6 +87,8 @@ class TLB : public BaseTLB
     TLB(const Params *p);
     virtual ~TLB();
 
+    virtual void regStats();
+
     int getsize() const { return size; }
 
     TlbEntry &index(bool advance = true);
@@ -116,50 +135,17 @@ class TLB : public BaseTLB
         EntryCache[0] = entry;
         return entry;
     }
-};
 
-class ITB : public TLB
-{
   protected:
-    mutable Stats::Scalar hits;
-    mutable Stats::Scalar misses;
-    mutable Stats::Scalar acv;
-    mutable Stats::Formula accesses;
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
 
   public:
-    typedef AlphaITBParams Params;
-    ITB(const Params *p);
-    virtual void regStats();
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-};
-
-class DTB : public TLB
-{
-  protected:
-    mutable Stats::Scalar read_hits;
-    mutable Stats::Scalar read_misses;
-    mutable Stats::Scalar read_acv;
-    mutable Stats::Scalar read_accesses;
-    mutable Stats::Scalar write_hits;
-    mutable Stats::Scalar write_misses;
-    mutable Stats::Scalar write_acv;
-    mutable Stats::Scalar write_accesses;
-    Stats::Formula hits;
-    Stats::Formula misses;
-    Stats::Formula acv;
-    Stats::Formula accesses;
-
-  public:
-    typedef AlphaDTBParams Params;
-    DTB(const Params *p);
-    virtual void regStats();
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc,
+            bool write = false, bool execute = false);
     void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write);
+            Translation *translation,
+            bool write = false, bool execute = false);
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 41d46c572..16cbe6879 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -36,21 +36,5 @@ from BaseTLB import BaseTLB
 
 class MipsTLB(BaseTLB):
     type = 'MipsTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class MipsDTB(MipsTLB):
-    type = 'MipsDTB'
-    cxx_class = 'MipsISA::DTB'
-    size = 64
-
-class MipsITB(MipsTLB):
-    type = 'MipsITB'
-    cxx_class = 'MipsISA::ITB'
-    size = 64
-
-class MipsUTB(MipsTLB):
-    type = 'MipsUTB'
-    cxx_class = 'MipsISA::UTB'
-    size = 64
-
+    cxx_class = 'MipsISA::TLB'
+    size = Param.Int(64, "TLB size")
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index eac44eba8..9343e35a3 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -45,10 +45,7 @@
 #include "cpu/thread_context.hh"
 #include "sim/process.hh"
 #include "mem/page_table.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
 #include "params/MipsTLB.hh"
-#include "params/MipsUTB.hh"
 
 
 using namespace std;
@@ -310,7 +307,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -426,16 +423,8 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 #endif
 }
 
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc), req, tc, false);
-}
-
 Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -572,61 +561,25 @@ DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 #endif
 }
 
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+        bool write, bool execute)
+{
+    if (execute)
+        return translateInst(req, tc);
+    else
+        return translateData(req, tc, write);
+}
+
 void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write, bool execute)
 {
     assert(translation);
-    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+    translation->finish(translateAtomic(req, tc, write, execute),
+            req, tc, write, execute);
 }
 
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips ITB
-//
-ITB::ITB(const Params *p)
-    : TLB(p)
-{}
-
-
-// void
-// ITB::regStats()
-// {
-//   /*    hits - causes failure for some reason
-//      .name(name() + ".hits")
-//      .desc("ITB hits");
-//     misses
-//      .name(name() + ".misses")
-//      .desc("ITB misses");
-//     acv
-//      .name(name() + ".acv")
-//      .desc("ITB acv");
-//     accesses
-//      .name(name() + ".accesses")
-//      .desc("ITB accesses");
-
-//      accesses = hits + misses + invalids; */
-// }
-
-
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips DTB
-//
-DTB::DTB(const Params *p)
-    : TLB(p)
-{}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips UTB
-//
-UTB::UTB(const Params *p)
-    : ITB(p), DTB(p)
-{}
-
-
 
 MipsISA::PTE &
 TLB::index(bool advance)
@@ -639,20 +592,8 @@ TLB::index(bool advance)
     return *pte;
 }
 
-MipsISA::ITB *
-MipsITBParams::create()
-{
-    return new MipsISA::ITB(this);
-}
-
-MipsISA::DTB *
-MipsDTBParams::create()
-{
-    return new MipsISA::DTB(this);
-}
-
-MipsISA::UTB *
-MipsUTBParams::create()
+MipsISA::TLB *
+MipsTLBParams::create()
 {
-    return new MipsISA::UTB(this);
+    return new MipsISA::TLB(this);
 }
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index dc0babf9a..fa2ed3f85 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -43,8 +43,7 @@
 #include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
+#include "params/MipsTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
@@ -138,34 +137,15 @@ class TLB : public BaseTLB
     void unserialize(Checkpoint *cp, const std::string &section);
 
     void regStats();
-};
-
-class ITB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-};
-
-class DTB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    DTB(const Params *p);
 
     Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-            bool write = false);
+            bool write=false, bool execute=false);
     void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef MipsTLBParams Params;
-    UTB(const Params *p);
+            Translation *translation, bool write=false, bool execute=false);
 
+  private:
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 };
 
 }
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 6758d612a..0c3fdc7fb 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -33,15 +33,5 @@ from BaseTLB import BaseTLB
 
 class SparcTLB(BaseTLB):
     type = 'SparcTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class SparcDTB(SparcTLB):
-    type = 'SparcDTB'
-    cxx_class = 'SparcISA::DTB'
-    size = 64
-
-class SparcITB(SparcTLB):
-    type = 'SparcITB'
-    cxx_class = 'SparcISA::ITB'
-    size = 64
+    cxx_class = 'SparcISA::TLB'
+    size = Param.Int(64, "TLB size")
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 95ad0229e..d11a41db5 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -67,6 +67,9 @@ TLB::TLB(const Params *p)
     cx_config = 0;
     sfsr = 0;
     tag_access = 0;
+    sfar = 0;
+    cacheEntry[0] = NULL;
+    cacheEntry[1] = NULL;
 }
 
 void
@@ -418,25 +421,17 @@ TLB::writeTagAccess(Addr va, int context)
 }
 
 void
-ITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
-{
-    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
-             (int)write, ct, ft, asi);
-    TLB::writeSfsr(write, ct, se, ft, asi);
-}
-
-void
-DTB::writeSfsr(Addr a, bool write, ContextType ct,
+TLB::writeSfsr(Addr a, bool write, ContextType ct,
         bool se, FaultTypes ft, int asi)
 {
-    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
+    DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
             a, (int)write, ct, ft, asi);
     TLB::writeSfsr(write, ct, se, ft, asi);
     sfar = a;
 }
 
 Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
@@ -450,10 +445,10 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 
     // Be fast if we can!
     if (cacheValid && cacheState == tlbdata) {
-        if (cacheEntry) {
-            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
-                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
-                req->setPaddr(cacheEntry->pte.translate(vaddr));
+        if (cacheEntry[0]) {
+            if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
+                cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
+                req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
                 return NoFault;
             }
         } else {
@@ -492,7 +487,7 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
     if ( hpriv || red ) {
         cacheValid = true;
         cacheState = tlbdata;
-        cacheEntry = NULL;
+        cacheEntry[0] = NULL;
         req->setPaddr(vaddr & PAddrImplMask);
         return NoFault;
     }
@@ -541,23 +536,15 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
     // cache translation date for next translation
     cacheValid = true;
     cacheState = tlbdata;
-    cacheEntry = e;
+    cacheEntry[0] = e;
 
     req->setPaddr(e->pte.translate(vaddr));
     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
     return NoFault;
 }
 
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc), req, tc, false);
-}
-
 Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
     /*
      * @todo this could really use some profiling and fixing to make
@@ -855,18 +842,29 @@ handleMmuRegAccess:
     return NoFault;
 };
 
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+        bool write, bool execute)
+{
+    if (execute)
+        return translateInst(req, tc);
+    else
+        return translateData(req, tc, write);
+}
+
 void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write, bool execute)
 {
     assert(translation);
-    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+    translation->finish(translateAtomic(req, tc, write, execute),
+            req, tc, write, execute);
 }
 
 #if FULL_SYSTEM
 
 Tick
-DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
     Addr va = pkt->getAddr();
     ASI asi = (ASI)pkt->req->getAsi();
@@ -875,7 +873,7 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
          (uint32_t)pkt->req->getAsi(), pkt->getAddr());
 
-    ITB *itb = tc->getITBPtr();
+    TLB *itb = tc->getITBPtr();
 
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
@@ -1051,7 +1049,7 @@ doMmuReadError:
 }
 
 Tick
-DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
     uint64_t data = gtoh(pkt->get<uint64_t>());
     Addr va = pkt->getAddr();
@@ -1071,7 +1069,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
          (uint32_t)asi, va, data);
 
-    ITB *itb = tc->getITBPtr();
+    TLB *itb = tc->getITBPtr();
 
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
@@ -1306,10 +1304,10 @@ doMmuWriteError:
 #endif
 
 void
-DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
+TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
-    ITB * itb = tc->getITBPtr();
+    TLB * itb = tc->getITBPtr();
     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
                 c0_tsb_ps0,
                 c0_config,
@@ -1333,7 +1331,7 @@ DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 }
 
 uint64_t
-DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
+TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
         uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
 {
     uint64_t tsb;
@@ -1391,6 +1389,7 @@ TLB::serialize(std::ostream &os)
         nameOut(os, csprintf("%s.PTE%d", name(), x));
         tlb[x].serialize(os);
     }
+    SERIALIZE_SCALAR(sfar);
 }
 
 void
@@ -1429,32 +1428,13 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
             lookupTable.insert(tlb[x].range, &tlb[x]);
 
     }
-}
-
-void
-DTB::serialize(std::ostream &os)
-{
-    TLB::serialize(os);
-    SERIALIZE_SCALAR(sfar);
-}
-
-void
-DTB::unserialize(Checkpoint *cp, const std::string &section)
-{
-    TLB::unserialize(cp, section);
     UNSERIALIZE_SCALAR(sfar);
 }
 
 /* end namespace SparcISA */ }
 
-SparcISA::ITB *
-SparcITBParams::create()
-{
-    return new SparcISA::ITB(this);
-}
-
-SparcISA::DTB *
-SparcDTBParams::create()
+SparcISA::TLB *
+SparcTLBParams::create()
 {
-    return new SparcISA::DTB(this);
+    return new SparcISA::TLB(this);
 }
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 4fe532d4a..cba60a0ff 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -36,8 +36,7 @@
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
-#include "params/SparcDTB.hh"
-#include "params/SparcITB.hh"
+#include "params/SparcTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 
@@ -57,6 +56,8 @@ class TLB : public BaseTLB
 
     //TLB state
   protected:
+    // Only used when this is the data TLB.
+    uint64_t sfar;
     uint64_t c0_tsb_ps0;
     uint64_t c0_tsb_ps1;
     uint64_t c0_config;
@@ -148,6 +149,9 @@ class TLB : public BaseTLB
 
     void writeTagAccess(Addr va, int context);
 
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+
   public:
     typedef SparcTLBParams Params;
     TLB(const Params *p);
@@ -159,52 +163,10 @@ class TLB : public BaseTLB
 
     void dumpAll();
 
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    /** Give an entry id, read that tlb entries' tte */
-    uint64_t TteRead(int entry);
-
-};
-
-class ITB : public TLB
-{
-  public:
-    typedef SparcITBParams Params;
-    ITB(const Params *p) : TLB(p)
-    {
-        cacheEntry = NULL;
-    }
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-  private:
-    void writeSfsr(bool write, ContextType ct,
-            bool se, FaultTypes ft, int asi);
-    TlbEntry *cacheEntry;
-    friend class DTB;
-};
-
-class DTB : public TLB
-{
-    //DTLB specific state
-  protected:
-    uint64_t sfar;
-  public:
-    typedef SparcDTBParams Params;
-    DTB(const Params *p) : TLB(p)
-    {
-        sfar = 0;
-        cacheEntry[0] = NULL;
-        cacheEntry[1] = NULL;
-    }
-
     Fault translateAtomic(RequestPtr req,
-            ThreadContext *tc, bool write=false);
+            ThreadContext *tc, bool write=false, bool execute=false);
     void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write=false);
+            Translation *translation, bool write=false, bool execute=false);
 #if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
@@ -215,6 +177,9 @@ class DTB : public TLB
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    /** Give an entry id, read that tlb entries' tte */
+    uint64_t TteRead(int entry);
+
   private:
     void writeSfsr(Addr a, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index f23fb8304..06098f58f 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -81,8 +81,8 @@ vtophys(ThreadContext *tc, Addr addr)
     //int sec_context = bits(tlbdata,63,48);
 
     FunctionalPort *mem = tc->getPhysPort();
-    ITB* itb = tc->getITBPtr();
-    DTB* dtb = tc->getDTBPtr();
+    TLB* itb = tc->getITBPtr();
+    TLB* dtb = tc->getDTBPtr();
     TlbEntry* tbe;
     PageTableEntry pte;
     Addr tsbs[4];
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index d5ae95372..15b03fd33 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -68,18 +68,8 @@ if build_env['FULL_SYSTEM']:
 
 class X86TLB(BaseTLB):
     type = 'X86TLB'
-    abstract = True
-    size = Param.Int("TLB size")
+    cxx_class = 'X86ISA::TLB'
+    size = Param.Int(64, "TLB size")
     if build_env['FULL_SYSTEM']:
         walker = Param.X86PagetableWalker(\
                 X86PagetableWalker(), "page table walker")
-
-class X86DTB(X86TLB):
-    type = 'X86DTB'
-    cxx_class = 'X86ISA::DTB'
-    size = 64
-
-class X86ITB(X86TLB):
-    type = 'X86ITB'
-    cxx_class = 'X86ISA::ITB'
-    size = 64
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index f625cf4bd..2471c0663 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -98,7 +98,7 @@ Walker::doNext(PacketPtr &write)
     bool uncacheable = pte.pcd;
     Addr nextRead = 0;
     bool doWrite = false;
-    bool badNX = pte.nx && (!tlb->allowNX() || !enableNX);
+    bool badNX = pte.nx && execute && enableNX;
     switch(state) {
       case LongPML4:
         DPRINTF(PageTableWalker,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 3fec4c7da..2feed6f3e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -700,55 +700,36 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
 };
 
 Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+        bool write, bool execute)
 {
     bool delayedResponse;
     return TLB::translate(req, tc, NULL, write,
-            false, delayedResponse, false);
+            execute, delayedResponse, false);
 }
 
 void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write, bool execute)
 {
     bool delayedResponse;
     assert(translation);
     Fault fault = TLB::translate(req, tc, translation,
-            write, false, delayedResponse, true);
+            write, execute, delayedResponse, true);
     if (!delayedResponse)
-        translation->finish(fault, req, tc, write);
-}
-
-Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
-{
-    bool delayedResponse;
-    return TLB::translate(req, tc, NULL, false,
-            true, delayedResponse, false);
-}
-
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
-{
-    bool delayedResponse;
-    assert(translation);
-    Fault fault = TLB::translate(req, tc, translation,
-            false, true, delayedResponse, true);
-    if (!delayedResponse)
-        translation->finish(fault, req, tc, false);
+        translation->finish(fault, req, tc, write, execute);
 }
 
 #if FULL_SYSTEM
 
 Tick
-DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
     return tc->getCpuPtr()->ticks(1);
 }
 
 Tick
-DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
     return tc->getCpuPtr()->ticks(1);
 }
@@ -765,28 +746,10 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
 {
 }
 
-void
-DTB::serialize(std::ostream &os)
-{
-    TLB::serialize(os);
-}
-
-void
-DTB::unserialize(Checkpoint *cp, const std::string &section)
-{
-    TLB::unserialize(cp, section);
-}
-
 /* end namespace X86ISA */ }
 
-X86ISA::ITB *
-X86ITBParams::create()
-{
-    return new X86ISA::ITB(this);
-}
-
-X86ISA::DTB *
-X86DTBParams::create()
+X86ISA::TLB *
+X86TLBParams::create()
 {
-    return new X86ISA::DTB(this);
+    return new X86ISA::TLB(this);
 }
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 2467bc472..f67a93d8d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -67,8 +67,7 @@
 #include "config/full_system.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
-#include "params/X86DTB.hh"
-#include "params/X86ITB.hh"
+#include "params/X86TLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
@@ -82,8 +81,6 @@ namespace X86ISA
 
     static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
 
-    class TLB;
-
     class TLB : public BaseTLB
     {
       protected:
@@ -91,14 +88,9 @@ namespace X86ISA
 
         typedef std::list<TlbEntry *> EntryList;
 
-        bool _allowNX;
         uint32_t configAddress;
 
       public:
-        bool allowNX() const
-        {
-            return _allowNX;
-        }
 
         typedef X86TLBParams Params;
         TLB(const Params *p);
@@ -140,45 +132,19 @@ namespace X86ISA
 
       public:
 
-        TlbEntry * insert(Addr vpn, TlbEntry &entry);
-
-        // Checkpointing
-        virtual void serialize(std::ostream &os);
-        virtual void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-    class ITB : public TLB
-    {
-      public:
-        typedef X86ITBParams Params;
-        ITB(const Params *p) : TLB(p)
-        {
-            _allowNX = false;
-        }
-
-        Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc,
+                bool write = false, bool execute = false);
         void translateTiming(RequestPtr req, ThreadContext *tc,
-                Translation *translation);
+                Translation *translation,
+                bool write = false, bool execute = false);
 
-        friend class DTB;
-    };
-
-    class DTB : public TLB
-    {
-      public:
-        typedef X86DTBParams Params;
-        DTB(const Params *p) : TLB(p)
-        {
-            _allowNX = true;
-        }
-        Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
-        void translateTiming(RequestPtr req, ThreadContext *tc,
-                Translation *translation, bool write);
 #if FULL_SYSTEM
         Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
         Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
 #endif
 
+        TlbEntry * insert(Addr vpn, TlbEntry &entry);
+
         // Checkpointing
         virtual void serialize(std::ostream &os);
         virtual void unserialize(Checkpoint *cp, const std::string &section);