mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

6 files changed, 24 insertions, 11 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5c2478946..a609b3ef9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -559,7 +559,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                       panic("Security Extensions not implemented!");
               }
               warn("Translating via MISCREG in atomic mode! Fix Me!\n");
-              req->setVirt(0, val, 1, flags, tc->pcState().pc());
+              req->setVirt(0, val, 1, flags, tc->pcState().pc(),
+                      Request::funcMasterId);
               fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
               if (fault == NoFault) {
                   miscRegs[MISCREG_PAR] =
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 9c92ebdf6..de3c38e78 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -52,6 +52,7 @@ using namespace ArmISA;
 
 TableWalker::TableWalker(const Params *p)
     : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
+      masterId(p->sys->getMasterId(name())),
       doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
 {
     sctlr = 0;
@@ -62,7 +63,6 @@ TableWalker::~TableWalker()
     ;
 }
 
-
 unsigned int
 TableWalker::drain(Event *de)
 {
@@ -239,7 +239,7 @@ TableWalker::processWalk()
         doL1Descriptor();
         f = currState->fault;
     } else {
-        RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag);
+        RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
         PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
         pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
         port->sendFunctional(pkt);
@@ -583,7 +583,7 @@ TableWalker::doL1Descriptor()
                     currState->tc->getCpuPtr()->ticks(1));
             doL2Descriptor();
         } else {
-            RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0);
+            RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId);
             PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
             pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
             port->sendFunctional(pkt);
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index d4a2e87b5..520bfd9ac 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -341,6 +341,9 @@ class TableWalker : public MemObject
     /** If a timing translation is currently in progress */
     bool pending;
 
+    /** Request id for requests generated by this walker */
+    MasterID masterId;
+
   public:
     typedef ArmTableWalkerParams Params;
     TableWalker(const Params *p);
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index f4a3ab9a6..4a165a4a1 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -80,7 +80,8 @@ namespace X86ISA
     prepIntRequest(const uint8_t id, Addr offset, Addr size)
     {
         RequestPtr req = new Request(x86InterruptAddress(id, offset),
-                                     size, Request::UNCACHEABLE);
+                                     size, Request::UNCACHEABLE,
+                                     Request::intMasterId);
         PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
         pkt->allocate();
         return pkt;
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 5b1730f0c..f29531cd5 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -499,7 +499,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
         Request::Flags flags = oldRead->req->getFlags();
         flags.set(Request::UNCACHEABLE, uncacheable);
         RequestPtr request =
-            new Request(nextRead, oldRead->getSize(), flags);
+            new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
         read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
         read->allocate();
         // If we need to write, adjust the read packet to write the modified
@@ -569,7 +569,7 @@ Walker::WalkerState::setupWalk(Addr vaddr)
     Request::Flags flags = Request::PHYSICAL;
     if (cr3.pcd)
         flags.set(Request::UNCACHEABLE);
-    RequestPtr request = new Request(topAddr, dataSize, flags);
+    RequestPtr request = new Request(topAddr, dataSize, flags, walker->masterId);
     read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
     read->allocate();
 }
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index 73e185148..d433c7b98 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -50,6 +50,7 @@
 #include "mem/packet.hh"
 #include "params/X86PagetableWalker.hh"
 #include "sim/faults.hh"
+#include "sim/system.hh"
 
 class ThreadContext;
 
@@ -67,7 +68,7 @@ namespace X86ISA
             {}
 
           protected:
-            Walker * walker;
+            Walker *walker;
 
             bool recvTiming(PacketPtr pkt);
             Tick recvAtomic(PacketPtr pkt);
@@ -97,7 +98,7 @@ namespace X86ISA
             };
 
           protected:
-            Walker * walker;
+            Walker *walker;
             ThreadContext *tc;
             RequestPtr req;
             State state;
@@ -115,7 +116,6 @@ namespace X86ISA
             bool timing;
             bool retrying;
             bool started;
-
           public:
             WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
                     RequestPtr _req, bool _isFunctional = false) :
@@ -172,6 +172,7 @@ namespace X86ISA
         // The TLB we're supposed to load.
         TLB * tlb;
         System * sys;
+        MasterID masterId;
 
         // Functions for dealing with packets.
         bool recvTiming(PacketPtr pkt);
@@ -187,9 +188,16 @@ namespace X86ISA
 
         typedef X86PagetableWalkerParams Params;
 
+        const Params *
+        params() const
+        {
+            return static_cast<const Params *>(_params);
+        }
+
         Walker(const Params *params) :
             MemObject(params), port(name() + ".port", this),
-            funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system)
+            funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
+            masterId(sys->getMasterId(name()))
         {
         }
     };