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author | Brandon Potter <brandon.potter@amd.com> | 2017-05-15 14:03:20 -0500 |
---|---|---|
committer | Brandon Potter <Brandon.Potter@amd.com> | 2017-05-18 16:34:52 +0000 |
commit | 9aadcc797263fc268fdd9f921ddffa473f56d78a (patch) | |
tree | ad2d9077f43cefb9dc6e8699376e3ca3a672e486 /src/arch | |
parent | 679a0e2ef1cc830c0de7e26ae1ff47df4d6e53b8 (diff) | |
download | gem5-9aadcc797263fc268fdd9f921ddffa473f56d78a.tar.xz |
syscall_emul, riscv: add override keyword to RISCV Process class
Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/riscv/process.hh | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh index f732a4436..2a27f350e 100644 --- a/src/arch/riscv/process.hh +++ b/src/arch/riscv/process.hh @@ -48,17 +48,19 @@ class RiscvProcess : public Process protected: RiscvProcess(ProcessParams * params, ObjectFile *objFile); - void initState(); + void initState() override; template<class IntType> void argsInit(int pageSize); public: - RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i); + RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; /// Explicitly import the otherwise hidden getSyscallArg using Process::getSyscallArg; - void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val); - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); + void setSyscallArg(ThreadContext *tc, int i, + RiscvISA::IntReg val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; virtual bool mmapGrowsDown() const override { return false; } }; |