fix comparing fp registers between legion and m5

make fp writes also chatty with the Sparc traceflag

src/arch/sparc/floatregfile.cc:
    make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
    fix comparing fp registers between legion and m5

--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714

1 files changed, 4 insertions, 0 deletions

diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc
index 1bb78c67b..6f04ca829 100644
--- a/src/arch/sparc/floatregfile.cc
+++ b/src/arch/sparc/floatregfile.cc
@@ -137,10 +137,12 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
       case SingleWidth:
         result32 = gtoh((uint32_t)val);
         memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+        DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
         break;
       case DoubleWidth:
         result64 = gtoh((uint64_t)val);
         memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+        DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");
@@ -163,10 +165,12 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
       case SingleWidth:
         result32 = gtoh((uint32_t)val);
         memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+        DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
         break;
       case DoubleWidth:
         result64 = gtoh((uint64_t)val);
         memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+        DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");