Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.

51 files changed, 57 insertions, 57 deletions

diff --git a/src/arch/alpha/mt.hh b/src/arch/alpha/mt.hh
index 88ab01e32..57cf90f79 100644
--- a/src/arch/alpha/mt.hh
+++ b/src/arch/alpha/mt.hh
@@ -66,6 +66,6 @@ getTargetThread(TC *tc)
     return 0;
 }
 
-}//namespace AlphaISA
+} // namespace AlphaISA
 
 #endif
diff --git a/src/arch/alpha/pagetable.cc b/src/arch/alpha/pagetable.cc
index 6640e72e2..4dff04777 100644
--- a/src/arch/alpha/pagetable.cc
+++ b/src/arch/alpha/pagetable.cc
@@ -61,4 +61,4 @@ TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(valid);
 }
 
-} //namespace AlphaISA
+} // namespace AlphaISA
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 614061ddd..58d54e790 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -595,7 +595,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-/* end namespace AlphaISA */ }
+} // namespace AlphaISA
 
 AlphaISA::TLB *
 AlphaTLBParams::create()
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index a68e7b2ef..6c1b223ab 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -246,6 +246,6 @@ static inline Fault genMachineCheckFault()
     return new Reset();
 }
 
-} // ArmISA namespace
+} // namespace ArmISA
 
 #endif // __ARM_FAULTS_HH__
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index a24852ba9..b2989e4b3 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -48,7 +48,7 @@
 #include "arch/arm/types.hh"
 #include "base/types.hh"
 
-namespace LittleEndianGuest {};
+namespace LittleEndianGuest {}
 
 #define TARGET_ARM
 
@@ -123,7 +123,7 @@ namespace ArmISA
         INT_FIQ,
         NumInterruptTypes
     };
-};
+} // namespace ArmISA
 
 using namespace ArmISA;
 
diff --git a/src/arch/arm/kernel_stats.hh b/src/arch/arm/kernel_stats.hh
index 18bdc500d..be5c25bd5 100644
--- a/src/arch/arm/kernel_stats.hh
+++ b/src/arch/arm/kernel_stats.hh
@@ -51,7 +51,7 @@ class Statistics : public ::Kernel::Statistics
     {}
 };
 
-} /* end namespace ArmISA::Kernel */
-} /* end namespace ArmISA */
+} // namespace ArmISA::Kernel
+} // namespace ArmISA
 
 #endif // __ARCH_ARM_KERNEL_STATS_HH__
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 75546f8de..531a6ee2e 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -192,7 +192,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     }
 }
 
-} /* namespace Trace */
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh
index 7467e3378..221d40e2f 100644
--- a/src/arch/arm/nativetrace.hh
+++ b/src/arch/arm/nativetrace.hh
@@ -107,6 +107,6 @@ class ArmNativeTrace : public NativeTrace
     void check(NativeTraceRecord *record);
 };
 
-} /* namespace Trace */
+} // namespace Trace
 
 #endif // __ARCH_ARM_NATIVETRACE_HH__
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 5b24eebe2..1374123b2 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -239,6 +239,6 @@ public:
     inline void invalidateMiscReg() { miscRegValid = false; }
 };
 
-/* namespace ArmISA */ }
+} // namespace ArmISA
 
 #endif // __ARCH_ARM_TLB_HH__
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index a3d6c1a8f..1cca51384 100755
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -199,6 +199,6 @@ void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign);
 void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
 uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
 
-} /* namespace MipsISA */
+} // namespace MipsISA
 
 #endif // __ARCH_MIPS_DSP_HH__
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 083aa5939..616886745 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -596,6 +596,6 @@ class DspStateDisabledFault : public MipsFault
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
-} // MipsISA namespace
+} // namespace MipsISA
 
 #endif // __MIPS_FAULTS_HH__
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index efb1fb594..648713926 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -39,7 +39,7 @@
 #include "base/types.hh"
 #include "config/full_system.hh"
 
-namespace LittleEndianGuest {};
+namespace LittleEndianGuest {}
 
 class StaticInstPtr;
 
@@ -164,6 +164,6 @@ const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 
-};
+} // namespace MipsISA
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/mips/kernel_stats.hh b/src/arch/mips/kernel_stats.hh
index f14c6f851..5cf6087c8 100644
--- a/src/arch/mips/kernel_stats.hh
+++ b/src/arch/mips/kernel_stats.hh
@@ -48,7 +48,7 @@ class Statistics : public ::Kernel::Statistics
 };
 
 
-} /* end namespace MipsISA::Kernel */
-} /* end namespace MipsISA */
+} // namespace MipsISA::Kernel
+} // namespace MipsISA
 
 #endif // __ARCH_MIPS_KERNEL_STATS_HH__
diff --git a/src/arch/mips/linux/threadinfo.hh b/src/arch/mips/linux/threadinfo.hh
index b0d0cd811..20a4033dd 100644
--- a/src/arch/mips/linux/threadinfo.hh
+++ b/src/arch/mips/linux/threadinfo.hh
@@ -148,6 +148,6 @@ class ThreadInfo
     }
 };
 
-/* namespace Linux */ }
+} // namespace Linux
 
 #endif // __ARCH_MIPS_LINUX_LINUX_THREADINFO_HH__
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index 0f49cc85d..f1977150c 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -98,6 +98,6 @@ genMachineCheckFault()
     return new MachineCheckFault();
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_FAULTS_HH__
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 7b9e78dee..1947e4ec3 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -236,6 +236,6 @@ class BranchRegCond : public BranchCond
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_BRANCH_HH__
diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
index a23667d9e..e5112b2c1 100644
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -81,6 +81,6 @@ class CondMoveOp : public PowerStaticInst
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_CONDITION_HH__
diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
index 2b2668409..deeac82cf 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -148,6 +148,6 @@ class FloatOp : public PowerStaticInst
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_FLOATING_HH__
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index b4b96d5dc..a7270cd38 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -171,6 +171,6 @@ class IntRotateOp : public IntShiftOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_INTEGER_HH__
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index 329dafe57..a58742690 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -86,6 +86,6 @@ class MemDispOp : public MemOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
index dd4941b93..d6a73d254 100644
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -52,6 +52,6 @@ class MiscOp : public PowerStaticInst
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_MISC_HH__
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index 91eca6fb0..48e5fa94b 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -71,6 +71,6 @@ class PowerStaticInst : public StaticInst
     }
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif //__ARCH_POWER_INSTS_STATICINST_HH__
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index ba1b5018d..78ae18ea9 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -110,6 +110,6 @@ class ISA
     }
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_HH__
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index ab6a56760..f0f50b9e9 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -38,7 +38,7 @@
 #include "arch/power/types.hh"
 #include "base/types.hh"
 
-namespace BigEndianGuest {};
+namespace BigEndianGuest {}
 
 class StaticInstPtr;
 
@@ -73,6 +73,6 @@ const ExtMachInst NoopMachInst = 0x60000000;
 // Memory accesses can be unaligned
 const bool HasUnalignedMemAcc = true;
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_TRAITS_HH__
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index 56ab1d4a0..6141b9ef2 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -59,6 +59,6 @@ handleLockedWrite(XC *xc, Request *req)
     return true;
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_LOCKED_MEM_HH__
diff --git a/src/arch/power/microcode_rom.hh b/src/arch/power/microcode_rom.hh
index e35db5112..0cb100653 100644
--- a/src/arch/power/microcode_rom.hh
+++ b/src/arch/power/microcode_rom.hh
@@ -40,6 +40,6 @@ namespace PowerISA
 
 using ::MicrocodeRom;
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_MICROCODE_ROM_HH__
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index 34732dad1..eba97d439 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -95,6 +95,6 @@ BitUnion32(Fpscr)
     Bitfield<2,1> rn;
 EndBitUnion(Fpscr)
 
-}; // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_MISCREGS_HH__
diff --git a/src/arch/power/mmaped_ipr.hh b/src/arch/power/mmaped_ipr.hh
index bd1ea10b3..fc88634dc 100644
--- a/src/arch/power/mmaped_ipr.hh
+++ b/src/arch/power/mmaped_ipr.hh
@@ -61,6 +61,6 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
     panic("No implementation for handleIprWrite in POWER\n");
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_MMAPED_IPR_HH__
diff --git a/src/arch/power/pagetable.cc b/src/arch/power/pagetable.cc
index 862404578..091fb8bc8 100644
--- a/src/arch/power/pagetable.cc
+++ b/src/arch/power/pagetable.cc
@@ -79,4 +79,4 @@ PTE::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(OffsetMask);
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index bd2b9d397..a5f18eba9 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -152,7 +152,7 @@ struct PTE
     void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_PAGETABLE_H__
 
diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh
index 431c5d1b7..8b1089095 100644
--- a/src/arch/power/predecoder.hh
+++ b/src/arch/power/predecoder.hh
@@ -120,6 +120,6 @@ class Predecoder
     }
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_PREDECODER_HH__
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 59816a599..8b2aefc47 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -101,6 +101,6 @@ enum MiscIntRegNums {
     INTREG_RSV_ADDR
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_REGISTERS_HH__
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 34bb4bd1f..b37c31713 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -79,6 +79,6 @@ class RemoteGDB : public BaseRemoteGDB
     }
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif /* __ARCH_POWER_REMOTE_GDB_H__ */
diff --git a/src/arch/power/stacktrace.hh b/src/arch/power/stacktrace.hh
index 49d687a6e..e87203df6 100644
--- a/src/arch/power/stacktrace.hh
+++ b/src/arch/power/stacktrace.hh
@@ -143,6 +143,6 @@ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
     return true;
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_STACKTRACE_HH__
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 8431b9ad1..7e5638cf1 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -167,6 +167,6 @@ class TLB : public BaseTLB
     void regStats();
 };
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_TLB_HH__
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index d049cdec1..61f8acfca 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -101,6 +101,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
     };
 };
 
-} // __hash_namespace namespace
+} // namespace __hash_namespace
 
 #endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index 399ec1f56..b02ccda08 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -62,4 +62,4 @@ skipFunction(ThreadContext *tc)
 }
 
 
-} // PowerISA namespace
+} // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index a47fcdc46..cbb9bb646 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,6 +78,6 @@ advancePC(PCState &pc, const StaticInstPtr inst)
     pc.advance();
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_UTILITY_HH__
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 3cfebcfc7..8b88c9215 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -51,7 +51,7 @@ PteAddr(Addr a)
     return (a & PteMask) << PteShift;
 }
 
-} // PowerISA namespace
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_VTOPHYS_HH__
 
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index e10e07494..bee29ee5e 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -302,6 +302,6 @@ genMachineCheckFault()
 }
 
 
-} // SparcISA namespace
+} // namespace SparcISA
 
 #endif // __SPARC_FAULTS_HH__
diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh
index c007c54c2..3d4c677a0 100644
--- a/src/arch/sparc/kernel_stats.hh
+++ b/src/arch/sparc/kernel_stats.hh
@@ -51,7 +51,7 @@ class Statistics : public ::Kernel::Statistics
     {}
 };
 
-} /* end namespace AlphaISA::Kernel */
-} /* end namespace AlphaISA */
+} // namespace AlphaISA::Kernel
+} // namespace AlphaISA
 
 #endif // __ARCH_SPARC_KERNEL_STATS_HH__
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index 5e3d5c8b3..7d8b96dc1 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -87,7 +87,7 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record)
     checkReg("ccr", regVal, realRegVal);
 }
 
-} /* namespace Trace */
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/sparc/nativetrace.hh b/src/arch/sparc/nativetrace.hh
index d618107bb..0bd40712b 100644
--- a/src/arch/sparc/nativetrace.hh
+++ b/src/arch/sparc/nativetrace.hh
@@ -47,6 +47,6 @@ class SparcNativeTrace : public NativeTrace
     void check(NativeTraceRecord *record);
 };
 
-} /* namespace Trace */
+} // namespace Trace
 
 #endif // __CPU_NATIVETRACE_HH__
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 512878499..7c7819561 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1408,7 +1408,7 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(sfar);
 }
 
-/* end namespace SparcISA */ }
+} // namespace SparcISA
 
 SparcISA::TLB *
 SparcTLBParams::create()
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index 48e778c6f..36b2557e7 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -129,4 +129,4 @@ vtophys(ThreadContext *tc, Addr addr)
     return pte.translate(addr);
 }
 
-} /* namespace SparcISA */
+} // namespace SparcISA
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 6b686f38a..fa5e30698 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -158,4 +158,4 @@ namespace X86ISA {
         }
         return true;
     }
-} //namespace X86ISA
+} // namespace X86ISA
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index 6f92cfacf..1999f6611 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -186,7 +186,7 @@ X86NativeTrace::check(NativeTraceRecord *record)
     checkXMM(15, mState.xmm, nState.xmm);
 }
 
-} /* namespace Trace */
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/x86/nativetrace.hh b/src/arch/x86/nativetrace.hh
index afa2a463d..c68f01455 100644
--- a/src/arch/x86/nativetrace.hh
+++ b/src/arch/x86/nativetrace.hh
@@ -85,6 +85,6 @@ class X86NativeTrace : public NativeTrace
     void check(NativeTraceRecord *record);
 };
 
-} /* namespace Trace */
+} // namespace Trace
 
 #endif // __ARCH_X86_NATIVETRACE_HH__
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ea737fa63..5882132e5 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -111,6 +111,6 @@ typedef union
 
 typedef uint16_t RegIndex;
 
-}; // namespace X86ISA
+} // namespace X86ISA
 
 #endif // __ARCH_X86_REGFILE_HH__
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 52d9cdf9c..7fa2e172c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -737,7 +737,7 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
 {
 }
 
-/* end namespace X86ISA */ }
+} // namespace X86ISA
 
 X86ISA::TLB *
 X86TLBParams::create()
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 88d5bfe58..756e9d526 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -243,4 +243,4 @@ skipFunction(ThreadContext *tc)
 }
 
 
-} //namespace X86_ISA
+} // namespace X86_ISA