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authorCiro Santilli <ciro.santilli@arm.com>2018-07-18 18:00:51 +0100
committerCiro Santilli <ciro.santilli@arm.com>2018-12-03 10:43:15 +0000
commit00ea41368d9364664ab6c9fc1e7a74bdffd8d41a (patch)
treea4e6764cb3f4a1a6fc1df88a7bdb17cc3d151e74 /src/arch
parentdb5ea632671383f102d61d2feda9976b2e036aa7 (diff)
downloadgem5-00ea41368d9364664ab6c9fc1e7a74bdffd8d41a.tar.xz
arch-arm: fix the aarch64 GDB stub
The main change is to remove vector registers from the GDB stub. Those registers were intended for SVE, which is a new architecture feature and not yet treated by default on the GDB present in Ubuntu 18.04, and possibly not even on GDB master. As a result, aarch64 GDB stub connections would fail with: Remote 'g' packet reply is too long The correct way to support those registers is to send XML GDB target description files to the client. This feature is not yet available for any architecture, and should be implemented in future patches. Other smaller fixes are: * cpsr is uint32_t in aarch64 as well as arm * use M5_ATTR_PACKED on the register structs since they are being cast and sent as byte arrays Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7 Reviewed-on: https://gem5-review.googlesource.com/c/14495 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/remote_gdb.cc8
-rw-r--r--src/arch/arm/remote_gdb.hh9
2 files changed, 4 insertions, 13 deletions
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index f1919372b..a395cd913 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -209,10 +209,6 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context)
r.v[i + 2] = context->readFloatRegBits(i + 0);
r.v[i + 3] = context->readFloatRegBits(i + 1);
}
-
- for (int i = 0; i < 32; i ++) {
- r.vec[i] = context->readVecReg(RegId(VecRegClass,i));
- }
}
void
@@ -235,10 +231,6 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
context->setFloatRegBits(i + 0, r.v[i + 2]);
context->setFloatRegBits(i + 1, r.v[i + 3]);
}
-
- for (int i = 0; i < 32; i ++) {
- context->setVecReg(RegId(VecRegClass, i), r.vec[i]);
- }
}
void
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index e5d50ee13..e59d7b045 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -51,7 +51,7 @@
#include <algorithm>
#include "arch/arm/utility.hh"
-#include "arch/generic/vec_reg.hh"
+#include "base/compiler.hh"
#include "base/remote_gdb.hh"
class System;
@@ -74,7 +74,7 @@ class RemoteGDB : public BaseRemoteGDB
uint32_t fpr[8*3];
uint32_t fpscr;
uint32_t cpsr;
- } r;
+ } M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }
@@ -95,10 +95,9 @@ class RemoteGDB : public BaseRemoteGDB
uint64_t x[31];
uint64_t spx;
uint64_t pc;
- uint64_t cpsr;
+ uint32_t cpsr;
uint32_t v[32*4];
- ArmISA::VecRegContainer vec[32];
- } r;
+ } M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }