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authorGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:27 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:27 -0500
commit043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (patch)
treeef8bab03f4260b67b57b00844d0245ca1e849ea0 /src/arch
parentdf05ffab1289b26aab2a0eb71ee55dcb7f42e5e9 (diff)
downloadgem5-043709fdfab3b6c46f6ef95d1f642cd3c06ee20a.tar.xz
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/SConscript3
-rw-r--r--src/arch/arm/isa.cc51
-rw-r--r--src/arch/arm/utility.cc14
3 files changed, 30 insertions, 38 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 70a8de7fb..775aa1f41 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -94,8 +94,7 @@ isa_parser = File('isa_parser.py')
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
cpu_models = list(env['CPU_MODELS'])
- if env['USE_CHECKER']:
- cpu_models.append('CheckerCPU')
+ cpu_models.append('CheckerCPU')
# Several files are generated from the ISA description.
# We always get the basic decoder and header file.
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b8a0fe282..a452991aa 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -39,17 +39,13 @@
*/
#include "arch/arm/isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
namespace ArmISA
{
@@ -294,11 +290,15 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
-#if USE_CHECKER
- tc->pcStateNoRecord(pc);
-#else
- tc->pcState(pc);
-#endif //USE_CHECKER
+
+ // Follow slightly different semantics if a CheckerCPU object
+ // is connected
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(pc);
+ } else {
+ tc->pcState(pc);
+ }
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
misc_reg < MISCREG_CP15_END) {
panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -401,14 +401,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
oc = sys->getThreadContext(x);
oc->getDTBPtr()->allCpusCaching();
oc->getITBPtr()->allCpusCaching();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it.
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getDTBPtr()->allCpusCaching();
checker->getITBPtr()->allCpusCaching();
}
-#endif
}
return;
}
@@ -426,14 +425,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAll();
oc->getDTBPtr()->flushAll();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it of a flush
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAll();
checker->getDTBPtr()->flushAll();
}
-#endif
}
return;
case MISCREG_ITLBIALL:
@@ -452,16 +450,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
bits(newVal, 7,0));
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIASIDIS:
@@ -472,14 +468,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIMVAAIS:
@@ -490,14 +483,12 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
}
-#endif
}
return;
case MISCREG_ITLBIMVA:
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 07932e676..28ffb6896 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -43,7 +43,7 @@
#include "arch/arm/tlb.hh"
#include "arch/arm/utility.hh"
#include "arch/arm/vtophys.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
@@ -118,11 +118,13 @@ skipFunction(ThreadContext *tc)
{
TheISA::PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
-#if USE_CHECKER
- tc->pcStateNoRecord(newPC);
-#else
- tc->pcState(newPC);
-#endif
+
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(newPC);
+ } else {
+ tc->pcState(newPC);
+ }
}
void