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authorChander Sudanthi <chander.sudanthi@arm.com>2012-06-05 01:23:10 -0400
committerChander Sudanthi <chander.sudanthi@arm.com>2012-06-05 01:23:10 -0400
commit15228694d0b5026dd0d86cb8fc233e025443ed92 (patch)
treedcc3cf9af69e08827c7b0176a52ef9045c1fc060 /src/arch
parent8a2ca2fd241a1019122578a875c917329710c930 (diff)
downloadgem5-15228694d0b5026dd0d86cb8fc233e025443ed92.tar.xz
ARM: removed extra white space
Extra white space fixes in miscregs.hh
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/miscregs.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 8fba5101b..0969479ee 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -351,7 +351,7 @@ namespace ArmISA
Bitfield<31> ie; // Instruction endianness
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
- Bitfield<28> tre; // TEX Remap bit
+ Bitfield<28> tre; // TEX Remap bit
Bitfield<27> nmfi;// Non-maskable fast interrupts enable
Bitfield<25> ee; // Exception Endianness bit
Bitfield<24> ve; // Interrupt vectors enable
@@ -369,10 +369,10 @@ namespace ArmISA
Bitfield<10> sw; // Enable swp/swpb
Bitfield<9,8> rs; // deprecated protection bits
Bitfield<6,3> rao4;// Read as one
- Bitfield<7> b; // Endianness support (unused)
+ Bitfield<7> b; // Endianness support (unused)
Bitfield<2> c; // Cache enable bit
Bitfield<1> a; // Alignment fault checking
- Bitfield<0> m; // MMU enable bit
+ Bitfield<0> m; // MMU enable bit
EndBitUnion(SCTLR)
BitUnion32(CPACR)