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authorAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
commit22c04190c607b9360d9a23548f8a54e83cf0e74a (patch)
tree576135962e3c9c725157b461c8009b05933bba2b /src/arch
parent735c4a87665119a33443cf8d191d329c66191c6e (diff)
downloadgem5-22c04190c607b9360d9a23548f8a54e83cf0e74a.tar.xz
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/isa.hh4
-rw-r--r--src/arch/alpha/kernel_stats.hh4
-rw-r--r--src/arch/alpha/pagetable.hh4
-rw-r--r--src/arch/alpha/process.hh2
-rw-r--r--src/arch/alpha/system.hh4
-rw-r--r--src/arch/alpha/tlb.hh4
-rw-r--r--src/arch/arm/isa_device.hh4
-rw-r--r--src/arch/arm/kvm/armv8_cpu.hh6
-rw-r--r--src/arch/arm/kvm/base_cpu.hh4
-rw-r--r--src/arch/arm/kvm/gic.hh20
-rw-r--r--src/arch/arm/pagetable.hh4
-rw-r--r--src/arch/arm/pmu.hh16
-rw-r--r--src/arch/arm/table_walker.hh4
-rw-r--r--src/arch/arm/tlb.hh8
-rw-r--r--src/arch/arm/types.hh9
-rw-r--r--src/arch/generic/types.hh16
-rwxr-xr-xsrc/arch/mips/interrupts.hh4
-rw-r--r--src/arch/mips/tlb.hh4
-rw-r--r--src/arch/power/tlb.hh4
-rw-r--r--src/arch/power/types.hh5
-rw-r--r--src/arch/sparc/interrupts.hh4
-rw-r--r--src/arch/sparc/isa.hh4
-rw-r--r--src/arch/sparc/system.hh4
-rw-r--r--src/arch/sparc/tlb.hh4
-rw-r--r--src/arch/x86/decoder.hh5
-rw-r--r--src/arch/x86/interrupts.hh4
-rw-r--r--src/arch/x86/isa.hh4
-rw-r--r--src/arch/x86/pagetable.hh4
-rw-r--r--src/arch/x86/regs/msr.hh5
-rw-r--r--src/arch/x86/tlb.hh4
-rw-r--r--src/arch/x86/types.hh5
-rw-r--r--src/arch/x86/utility.hh1
32 files changed, 88 insertions, 90 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 6a88ee40b..6c06fc397 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -92,8 +92,8 @@ namespace AlphaISA
memset(ipr, 0, sizeof(ipr));
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
int
flattenIntIndex(int reg) const
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
index 188d3ec4b..06d20e6fa 100644
--- a/src/arch/alpha/kernel_stats.hh
+++ b/src/arch/alpha/kernel_stats.hh
@@ -86,8 +86,8 @@ class Statistics : public ::Kernel::Statistics
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 0b6524043..dc13d3790 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -142,8 +142,8 @@ struct TlbEntry : public Serializable
return ppn << PageShift;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace AlphaISA
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index 6701017e0..cd45871b1 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -42,7 +42,7 @@ class AlphaLiveProcess : public LiveProcess
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void loadState(CheckpointIn &cp) override;
void initState();
void argsInit(int intSize, int pageSize);
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 3f4a2367e..f8ca54506 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -60,8 +60,8 @@ class AlphaSystem : public System
/**
* Serialization stuff
*/
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** Override startup() to provide a path to call setupFuncEvents()
*/
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 73ffda1f6..a8bdf30e1 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -117,8 +117,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// Most recently used page table entries
TlbEntry *EntryCache[3];
diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh
index 8b12fa502..185e632a5 100644
--- a/src/arch/arm/isa_device.hh
+++ b/src/arch/arm/isa_device.hh
@@ -97,8 +97,8 @@ class DummyISADevice : public BaseISADevice
: BaseISADevice() {}
~DummyISADevice() {}
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
+ MiscReg readMiscReg(int misc_reg) override;
};
}
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 97127b471..aee27a8a4 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -83,11 +83,11 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
- void updateKvmState() M5_ATTR_OVERRIDE;
- void updateThreadContext() M5_ATTR_OVERRIDE;
+ void updateKvmState() override;
+ void updateThreadContext() override;
protected:
/** Mapping between integer registers in gem5 and KVM */
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 736153b78..2f6f978f7 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -52,10 +52,10 @@ class BaseArmKvmCPU : public BaseKvmCPU
BaseArmKvmCPU(BaseArmKvmCPUParams *params);
virtual ~BaseArmKvmCPU();
- void startup() M5_ATTR_OVERRIDE;
+ void startup() override;
protected:
- Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE;
+ Tick kvmRun(Tick ticks) override;
/** Cached state of the IRQ line */
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 4a115c87c..f156caa6b 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -76,23 +76,23 @@ class KvmGic : public BaseGic
KvmGic(const KvmGicParams *p);
~KvmGic();
- void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
- void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+ void startup() override { verifyMemoryMode(); }
+ void drainResume() override { verifyMemoryMode(); }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(Checkpoint *cp, const std::string &sec) override;
public: // PioDevice
AddrRangeList getAddrRanges() const { return addrRanges; }
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
public: // BaseGic
- void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
- void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+ void sendInt(uint32_t num) override;
+ void clearInt(uint32_t num) override;
- void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
- void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+ void sendPPInt(uint32_t num, uint32_t cpu) override;
+ void clearPPInt(uint32_t num, uint32_t cpu) override;
protected:
/**
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 3de993d27..6d306d6e0 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -284,7 +284,7 @@ struct TlbEntry : public Serializable
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(longDescFormat);
SERIALIZE_SCALAR(pfn);
@@ -314,7 +314,7 @@ struct TlbEntry : public Serializable
paramOut(cp, "domain", domain_);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(longDescFormat);
UNSERIALIZE_SCALAR(pfn);
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 80be965a4..fc5bf74b3 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -96,10 +96,10 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
public: // SimObject and related interfaces
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public: // ISA Device interface
@@ -109,14 +109,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
* @param misc_reg Register number (see miscregs.hh)
* @param val Value to store
*/
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
/**
* Read a register within the PMU.
*
* @param misc_reg Register number (see miscregs.hh)
* @return Register value.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ MiscReg readMiscReg(int misc_reg) override;
protected: // PMU register types and constants
BitUnion32(PMCR_t)
@@ -269,7 +269,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
: ProbeListenerArgBase(pm, name),
pmu(_pmu), id(_id) {}
- void notify(const uint64_t &val) M5_ATTR_OVERRIDE
+ void notify(const uint64_t &val) override
{
pmu.handleEvent(id, val);
}
@@ -329,8 +329,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
listeners.reserve(4);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Add an event count to the counter and check for overflow.
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index e973e9a74..8af70075d 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -891,8 +891,8 @@ class TableWalker : public MemObject
bool haveLargeAsid64() const { return _haveLargeAsid64; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
- DrainState drain() M5_ATTR_OVERRIDE;
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ virtual void drainResume() override;
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 35049db48..f6776b0a9 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -284,15 +284,15 @@ class TLB : public BaseTLB
bool callFromS2);
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/**
* Get the table walker master port. This is used for migrating
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index c54bfb5f4..29828be75 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
@@ -483,7 +482,7 @@ namespace ArmISA
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
@@ -494,7 +493,7 @@ namespace ArmISA
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
@@ -740,7 +739,7 @@ namespace ArmISA
} // namespace ArmISA
-__hash_namespace_begin
+namespace std {
template<>
struct hash<ArmISA::ExtMachInst> :
@@ -752,6 +751,6 @@ struct hash<ArmISA::ExtMachInst> :
};
-__hash_namespace_end
+}
#endif
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 8e35b5b2f..2de8ca7b4 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -105,14 +105,14 @@ class PCStateBase : public Serializable
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(_pc);
SERIALIZE_SCALAR(_npc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(_pc);
UNSERIALIZE_SCALAR(_npc);
@@ -248,7 +248,7 @@ class UPCState : public SimplePCState<MachInst>
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
@@ -256,7 +256,7 @@ class UPCState : public SimplePCState<MachInst>
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
@@ -329,14 +329,14 @@ class DelaySlotPCState : public SimplePCState<MachInst>
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_nnpc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_nnpc);
@@ -426,7 +426,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
@@ -434,7 +434,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 3c9165bfa..b5323e4e1 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -116,13 +116,13 @@ class Interrupts : public SimObject
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
fatal("Serialization of Interrupts Unimplemented for MIPS");
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
fatal("Unserialization of Interrupts Unimplemented for MIPS");
}
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 5a9069e4c..a2f356e1f 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -107,8 +107,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index a07dad954..81ea22cc4 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -172,8 +172,8 @@ class TLB : public BaseTLB
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
};
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index a5d204827..83917ec0c 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -33,7 +33,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
namespace PowerISA
@@ -89,7 +88,7 @@ typedef GenericISA::SimplePCState<MachInst> PCState;
} // PowerISA namespace
-__hash_namespace_begin
+namespace std {
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
@@ -98,6 +97,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
};
};
-__hash_namespace_end
+}
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 432132f66..8929759f3 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -191,14 +191,14 @@ class Interrupts : public SimObject
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 1d2a457d2..18ac30857 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -167,8 +167,8 @@ class ISA : public SimObject
void clear();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc) {}
diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index 68688cc1f..68a192cb9 100644
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -54,8 +54,8 @@ class SparcSystem : public System
* Serialization stuff
*/
public:
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** reset binary symbol table */
SymbolTable *resetSymtab;
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e64d3f1b4..cd4634ab8 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -176,8 +176,8 @@ class TLB : public BaseTLB
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Give an entry id, read that tlb entries' tte */
uint64_t TteRead(int entry);
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index d42751d21..2e5e83764 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -32,6 +32,7 @@
#define __ARCH_X86_DECODER_HH__
#include <cassert>
+#include <unordered_map>
#include <vector>
#include "arch/x86/regs/misc.hh"
@@ -223,11 +224,11 @@ class Decoder
typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
DecodePages *decodePages;
- typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
+ typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
AddrCacheMap addrCacheMap;
DecodeCache::InstMap *instMap;
- typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
+ typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
static InstCacheMap instCacheMap;
public:
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 272cfea44..b1bdbf10f 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -293,8 +293,8 @@ class Interrupts : public BasicPioDevice, IntDevice
/*
* Serialization.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/*
* Old functions needed for compatability but which will be phased out
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 88f4980ae..90ab619cc 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -97,8 +97,8 @@ namespace X86ISA
return reg;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc);
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 3345366d0..1361109d5 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -149,8 +149,8 @@ namespace X86ISA
return (1 << logBytes);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/** The size of each level of the page table expressed in base 2
diff --git a/src/arch/x86/regs/msr.hh b/src/arch/x86/regs/msr.hh
index a2ae5c69a..f273a8227 100644
--- a/src/arch/x86/regs/msr.hh
+++ b/src/arch/x86/regs/msr.hh
@@ -31,14 +31,15 @@
#ifndef __ARCH_X86_REG_MSR_HH__
#define __ARCH_X86_REG_MSR_HH__
+#include <unordered_map>
+
#include "arch/x86/regs/misc.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
namespace X86ISA
{
-typedef m5::hash_map<Addr, MiscRegIndex> MsrMap;
+typedef std::unordered_map<Addr, MiscRegIndex> MsrMap;
/**
* Map between MSR addresses and their corresponding misc registers.
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 83ec7cc59..6e3eb2eee 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -148,8 +148,8 @@ namespace X86ISA
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Get the table walker master port. This is used for
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 88b000b6e..99e2c826c 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/cprintf.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
@@ -346,7 +345,7 @@ namespace X86ISA
}
-__hash_namespace_begin
+namespace std {
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
@@ -362,7 +361,7 @@ __hash_namespace_begin
emi.stackSize ^ emi.dispSize;
};
};
-__hash_namespace_end
+}
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
// and UNSERIALIZE_SCALAR.
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9be66d8d2..87bed9762 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -42,7 +42,6 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"