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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-01 15:33:06 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-13 09:24:57 +0000 |
| commit | 2bc7810cfc4feba7bd320cc65c78a3351dff5e3f (patch) | |
| tree | cf750929da236adf577fc6d98304d6fc4c850159 /src/arch | |
| parent | 0a67a7a7ce42fd1af0f5013b9723126e18f45378 (diff) | |
| download | gem5-2bc7810cfc4feba7bd320cc65c78a3351dff5e3f.tar.xz | |
arch-arm: Corrected encoding for T32 HVC instruction
This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 513506d31..df85b08a7 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010, 2012-2013 ARM Limited +// Copyright (c) 2010,2012-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -247,7 +247,7 @@ def format Thumb32BranchesAndMiscCtrl() {{ } } } - case 0xfe: + case 0x7e: { uint32_t imm16 = (bits(machInst, 19, 16) << 12) | (bits(machInst, 11, 0) << 0); |