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authorGabe Black <gblack@eecs.umich.edu>2009-07-10 01:21:04 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-10 01:21:04 -0700
commit60577eb4caff66a756f260bff6bf3bf8cb7edcba (patch)
tree339d0ac0dc4791aed93fad1afe3d1819badcbdb0 /src/arch
parent64fe7af51a4cfd01886bf524f4f37d7e1a31fa9f (diff)
downloadgem5-60577eb4caff66a756f260bff6bf3bf8cb7edcba.tar.xz
ISAs: Get rid of the IControl operand type.
A separate operand type is not necessary to use two bitfields to generate the index.
Diffstat (limited to 'src/arch')
-rwxr-xr-xsrc/arch/isa_parser.py44
-rw-r--r--src/arch/mips/isa/operands.isa5
2 files changed, 1 insertions, 48 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 4c4a26bcf..6f002c05b 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1267,9 +1267,6 @@ class Operand(object):
def isControlReg(self):
return 0
- def isIControlReg(self):
- return 0
-
def getFlags(self):
# note the empty slice '[:]' gives us a copy of self.flags[0]
# instead of a reference to it
@@ -1434,47 +1431,6 @@ class ControlRegOperand(Operand):
self.base_name
return wb
-class IControlRegOperand(Operand):
- def isReg(self):
- return 1
-
- def isIControlReg(self):
- return 1
-
- def makeConstructor(self):
- c = ''
- if self.is_src:
- c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
- (self.src_reg_idx, self.reg_spec)
- if self.is_dest:
- c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
- (self.dest_reg_idx, self.reg_spec)
- return c
-
- def makeRead(self):
- bit_select = 0
- if (self.ctype == 'float' or self.ctype == 'double'):
- error(0, 'Attempt to read control register as FP')
- if self.read_code != None:
- return self.buildReadCode('readMiscReg')
- base = 'xc->readMiscReg(%s)' % self.reg_spec
- if self.size == self.dflt_size:
- return '%s = %s;\n' % (self.base_name, base)
- else:
- return '%s = bits(%s, %d, 0);\n' % \
- (self.base_name, base, self.size-1)
-
- def makeWrite(self):
- if (self.ctype == 'float' or self.ctype == 'double'):
- error(0, 'Attempt to write control register as FP')
- if self.write_code != None:
- return self.buildWriteCode('setMiscReg')
- wb = 'xc->setMiscReg(%s, %s);\n' % \
- (self.reg_spec, self.base_name)
- wb += 'if (traceData) { traceData->setData(%s); }' % \
- self.base_name
- return wb
-
class ControlBitfieldOperand(ControlRegOperand):
def makeRead(self):
bit_select = 0
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 609708a13..c2733be9d 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -113,10 +113,7 @@ def operands {{
'Index':('ControlReg','uw','MipsISA::Index',None,1),
- #Special cases for when a Control Register Access is dependent on
- #a combination of bitfield indices (handles MTCO & MFCO)
- # Fixed to allow CP0 Register Offset
- 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
+ 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
#MT Control Regs
'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),