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authorAkash Bagdia <akash.bagdia@ARM.com>2014-09-02 11:26:32 +0100
committerAkash Bagdia <akash.bagdia@ARM.com>2014-09-02 11:26:32 +0100
commit8b7724d04c8bd337c096ac4364beceac6a64cde2 (patch)
tree26a81a50175bdd7bd8fc66de94efed706f4a12a4 /src/arch
parentd6f1c6ce89c16eda7d86c319cc92f551ee352496 (diff)
downloadgem5-8b7724d04c8bd337c096ac4364beceac6a64cde2.tar.xz
arm: Don't speculatively access most miscregisters.
Speculative exeuction can cause panics in detailed execution mode that shouldn't happen.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/insts/misc.isa2
-rw-r--r--src/arch/arm/miscregs.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 5403ddc8d..6ecaa78de 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -219,7 +219,7 @@ let {{
msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
{ "code": msrBankedRegCode,
"predicate_test": predicateTest },
- ["IsSerializeAfter"])
+ ["IsSerializeAfter", "IsNonSpeculative"])
header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
exec_output += PredOpExecute.subst(msrBankedRegIop)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d682dc454..c54e7d07b 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -758,7 +758,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
// MISCREG_CNTP_CVAL
bitset<NUM_MISCREG_INFOS>(string("0000000000000001001")),
// MISCREG_CNTP_CVAL_NS
- bitset<NUM_MISCREG_INFOS>(string("1100110011111110000")),
+ bitset<NUM_MISCREG_INFOS>(string("1100110011111110001")),
// MISCREG_CNTP_CVAL_S
bitset<NUM_MISCREG_INFOS>(string("0011001100111110000")),
// MISCREG_CNTV_CVAL