cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

31 files changed, 156 insertions, 92 deletions

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 6c06fc397..80d8ab149 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -38,6 +38,7 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
@@ -95,6 +96,8 @@ namespace AlphaISA
         void serialize(CheckpointOut &cp) const override;
         void unserialize(CheckpointIn &cp) override;
 
+        RegId flattenRegId(const RegId& regId) const { return regId; }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index d4b6db043..a43efff9c 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -130,7 +130,7 @@ output decoder {{
     Jump::branchTarget(ThreadContext *tc) const
     {
         PCState pc = tc->pcState();
-        uint64_t Rb = tc->readIntReg(_srcRegIdx[0].regIdx);
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0].index());
         pc.set((Rb & ~3) | (pc.pc() & 1));
         return pc;
     }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index afece988f..6213c8e08 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -149,7 +149,7 @@ output decoder {{
 
 #ifndef SS_COMPATIBLE_DISASSEMBLY
         std::string suffix("");
-        suffix += ((_destRegIdx[0].regClass == FloatRegClass)
+        suffix += ((_destRegIdx[0].isFloatReg())
                    ? fpTrappingModeSuffix[trappingMode]
                    : intTrappingModeSuffix[trappingMode]);
         suffix += roundingModeSuffix[roundingMode];
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index e75cec524..34e2cb5ad 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -246,11 +246,11 @@ output decoder {{
     void
     AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
     {
-        if (reg.regClass == IntRegClass) {
-            ccprintf(os, "r%d", reg.regIdx);
+        if (reg.isIntReg()) {
+            ccprintf(os, "r%d", reg.index());
         }
         else {
-            ccprintf(os, "f%d", reg.regIdx);
+            ccprintf(os, "f%d", reg.index());
         }
     }
 
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 0114a4aba..059f86f63 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -51,16 +51,16 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     ss << ", ";
     bool foundPsr = false;
     for (unsigned i = 0; i < numSrcRegs(); i++) {
-        RegId reg = srcRegIdx(i);
-        if (reg.regClass != MiscRegClass) {
+        const RegId& reg = srcRegIdx(i);
+        if (!reg.isMiscReg()) {
             continue;
         }
-        if (reg.regIdx == MISCREG_CPSR) {
+        if (reg.index() == MISCREG_CPSR) {
             ss << "cpsr";
             foundPsr = true;
             break;
         }
-        if (reg.regIdx == MISCREG_SPSR) {
+        if (reg.index() == MISCREG_SPSR) {
             ss << "spsr";
             foundPsr = true;
             break;
@@ -79,16 +79,16 @@ MsrBase::printMsrBase(std::ostream &os) const
     bool apsr = false;
     bool foundPsr = false;
     for (unsigned i = 0; i < numDestRegs(); i++) {
-        RegId reg = destRegIdx(i);
-        if (reg.regClass != MiscRegClass) {
+        const RegId& reg = destRegIdx(i);
+        if (!reg.isMiscReg()) {
             continue;
         }
-        if (reg.regIdx == MISCREG_CPSR) {
+        if (reg.index() == MISCREG_CPSR) {
             os << "cpsr_";
             foundPsr = true;
             break;
         }
-        if (reg.regIdx == MISCREG_SPSR) {
+        if (reg.index() == MISCREG_SPSR) {
             if (bits(byteMask, 1, 0)) {
                 os << "spsr_";
             } else {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index e05f0e18a..8de90dc93 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -177,6 +177,22 @@ namespace ArmISA
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
         void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
 
+        RegId
+        flattenRegId(const RegId& regId) const
+        {
+            switch (regId.classValue()) {
+              case IntRegClass:
+                return RegId(IntRegClass, flattenIntIndex(regId.index()));
+              case FloatRegClass:
+                return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+              case CCRegClass:
+                return RegId(CCRegClass, flattenCCIndex(regId.index()));
+              case MiscRegClass:
+                return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+            }
+            return RegId();
+        }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index d60dc60f1..48fc87ccb 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -328,7 +328,7 @@ let {{
 
     buildDataXImmInst("mrs", '''
         MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
-            flattenMiscIndex(op1);
+            flattenRegId(RegId(MiscRegClass, op1)).index();
         CPSR cpsr = Cpsr;
         ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
         %s
@@ -346,7 +346,7 @@ let {{
 
     buildDataXImmInst("msr", '''
         MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
-            flattenMiscIndex(dest);
+            flattenRegId(RegId(MiscRegClass, dest)).index();
         CPSR cpsr = Cpsr;
         ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
         %s
@@ -362,7 +362,8 @@ let {{
     ''')
 
     msrdczva_ea_code = '''
-        MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
+        MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
+                                   RegId(MiscRegClass, dest)).index();
         CPSR cpsr = Cpsr;
         ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
     '''
@@ -391,7 +392,8 @@ let {{
 
     buildDataXImmInst("msrSP", '''
         if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+                (MiscRegIndex) xc->tcBase()->flattenRegId(
+                   RegId(MiscRegClass, dest)).index(),
                 Scr64, Cpsr, xc->tcBase())) {
             return std::make_shared<UndefinedInstruction>(machInst, false,
                                                           mnemonic);
@@ -401,7 +403,8 @@ let {{
 
     buildDataXImmInst("msrDAIFSet", '''
         if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+                (MiscRegIndex) xc->tcBase()->flattenRegId(
+                   RegId(MiscRegClass, dest)).index(),
                 Scr64, Cpsr, xc->tcBase())) {
             return std::make_shared<UndefinedInstruction>(
                             machInst, 0, EC_TRAPPED_MSR_MRS_64,
@@ -414,7 +417,8 @@ let {{
 
     buildDataXImmInst("msrDAIFClr", '''
         if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+                (MiscRegIndex) xc->tcBase()->flattenRegId(
+                   RegId(MiscRegClass, dest)).index(),
                 Scr64, Cpsr, xc->tcBase())) {
             return std::make_shared<UndefinedInstruction>(
                                 machInst, 0, EC_TRAPPED_MSR_MRS_64,
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index dc2f30701..dff906755 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -224,7 +224,7 @@ let {{
     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
         HCR hcr = Hcr;
         bool hypTrap = false;
-        switch(xc->tcBase()->flattenMiscIndex(op1)) {
+        switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) {
           case MISCREG_FPSID:
             hypTrap = hcr.tid0;
             break;
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 6d6e56b8f..5eda615b5 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -813,7 +813,8 @@ let {{
     exec_output += PredOpExecute.subst(bfiIop)
 
     mrc14code = '''
-    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
+    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
+                               RegId(MiscRegClass, op1)).index();
     bool can_read, undefined;
     std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
     if (!can_read || undefined) {
@@ -837,7 +838,8 @@ let {{
 
 
     mcr14code = '''
-    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
+    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
+                               RegId(MiscRegClass, dest)).index();
     bool can_write, undefined;
     std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
     if (undefined || !can_write) {
@@ -862,7 +864,8 @@ let {{
     mrc15code = '''
     int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
-                           xc->tcBase()->flattenMiscIndex(preFlatOp1);
+                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+                                                      preFlatOp1)).index();
     bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
                                      Hcptr, imm);
     bool can_read, undefined;
@@ -893,7 +896,8 @@ let {{
     mcr15code = '''
     int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
-                       xc->tcBase()->flattenMiscIndex(preFlatDest);
+                       xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+                                                  preFlatDest)).index();
     bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
                                       Hcptr, imm);
     bool can_write, undefined;
@@ -925,7 +929,8 @@ let {{
     mrrc15code = '''
     int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
-                           xc->tcBase()->flattenMiscIndex(preFlatOp1);
+                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+                                                      preFlatOp1)).index();
     bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
     bool can_read, undefined;
     std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
@@ -955,7 +960,8 @@ let {{
     mcrr15code = '''
     int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
-                           xc->tcBase()->flattenMiscIndex(preFlatDest);
+                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+                                                      preFlatDest)).index();
     bool hypTrap  = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
     bool can_write, undefined;
     std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index feb55e473..c751cb168 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -37,6 +37,7 @@
 
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
+#include "cpu/reg_class.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 
@@ -165,6 +166,8 @@ namespace MipsISA
 
         ISA(Params *p);
 
+        RegId flattenRegId(const RegId& regId) const { return regId; }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index c0f259666..946dce6df 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -72,11 +72,11 @@ output decoder {{
 
     void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
     {
-        if (reg.regClass == IntRegClass) {
-            ccprintf(os, "r%d", reg.regIdx);
+        if (reg.isIntReg()) {
+            ccprintf(os, "r%d", reg.index());
         }
         else {
-            ccprintf(os, "f%d", reg.regIdx);
+            ccprintf(os, "f%d", reg.index());
         }
     }
 
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 641608e89..c21c1255b 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -257,9 +257,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }
 
@@ -272,9 +272,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }
 
@@ -287,9 +287,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }
 
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index f10e8453a..d13a0a7d3 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc,
 PowerISA::PCState
 BranchRegCond::branchTarget(ThreadContext *tc) const
 {
-    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx);
+    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
     return regVal & 0xfffffffc;
 }
 
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 210205db2..85f9cf628 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -38,15 +38,12 @@ using namespace PowerISA;
 void
 PowerStaticInst::printReg(std::ostream &os, RegId reg) const
 {
-    switch (reg.regClass) {
-      case IntRegClass:
-        ccprintf(os, "r%d", reg.regIdx);
-        break;
-      case FloatRegClass:
-        ccprintf(os, "f%d", reg.regIdx);
-        break;
-      case MiscRegClass:
-        switch (reg.regIdx) {
+    if (reg.isIntReg())
+        ccprintf(os, "r%d", reg.index());
+    else if (reg.isFloatReg())
+        ccprintf(os, "f%d", reg.index());
+    else if (reg.isMiscReg())
+        switch (reg.index()) {
           case 0: ccprintf(os, "cr"); break;
           case 1: ccprintf(os, "xer"); break;
           case 2: ccprintf(os, "lr"); break;
@@ -54,9 +51,8 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const
           default: ccprintf(os, "unknown_reg");
             break;
         }
-      case CCRegClass:
+    else if (reg.isCCReg())
         panic("printReg: POWER does not implement CCRegClass\n");
-    }
 }
 
 std::string
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index aaf5bd92a..475b4d2f8 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -36,6 +36,7 @@
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/misc.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
 struct PowerISAParams;
@@ -86,6 +87,8 @@ class ISA : public SimObject
         fatal("Power does not currently have any misc regs defined\n");
     }
 
+    RegId flattenRegId(const RegId& regId) const { return regId; }
+
     int
     flattenIntIndex(int reg) const
     {
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index d2f38b158..3f2412303 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -44,6 +44,7 @@
 #include "arch/riscv/registers.hh"
 #include "arch/riscv/types.hh"
 #include "base/misc.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
 struct RiscvISAParams;
@@ -78,6 +79,12 @@ class ISA : public SimObject
     void
     setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
 
+    RegId
+    flattenRegId(const RegId &regId) const
+    {
+        return regId;
+    }
+
     int
     flattenIntIndex(int reg) const
     {
diff --git a/src/arch/riscv/isa/base.isa b/src/arch/riscv/isa/base.isa
index dafccc981..a7e2fc954 100644
--- a/src/arch/riscv/isa/base.isa
+++ b/src/arch/riscv/isa/base.isa
@@ -70,13 +70,12 @@ output decoder {{
     std::string
     RiscvStaticInst::regName(RegId reg) const
     {
-        switch (reg.regClass) {
-          case IntRegClass:
-            return std::string(RegisterNames[reg.regIdx]);
-          case FloatRegClass:
-            return std::string("f") + std::to_string(reg.regIdx);
-          default:
-            return csprintf("unknown[%i/%i]", reg.regClass, reg.regIdx);
+        if (reg.isIntReg()) {
+            return std::string(RegisterNames[reg.index()]);
+        } else if (reg.isFloatReg()) {
+            return std::string("f") + std::to_string(reg.index());
+        } else {
+            return csprintf("%s{%i}", reg.className(), reg.index());
         }
     }
 }};
diff --git a/src/arch/riscv/isa/formats/type.isa b/src/arch/riscv/isa/formats/type.isa
index 0f2ffe9c4..f6a563699 100644
--- a/src/arch/riscv/isa/formats/type.isa
+++ b/src/arch/riscv/isa/formats/type.isa
@@ -210,7 +210,7 @@ output decoder {{
     Jump::branchTarget(ThreadContext *tc) const
     {
         PCState pc = tc->pcState();
-        IntReg Rs1 = tc->readIntReg(_srcRegIdx[0].regIdx);
+        IntReg Rs1 = tc->readIntReg(_srcRegIdx[0].index());
         pc.set((Rs1 + imm)&~0x1);
         return pc;
     }
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 18ac30857..ded5b34ff 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -37,6 +37,7 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
 class Checkpoint;
@@ -189,6 +190,22 @@ class ISA : public SimObject
     void setMiscReg(int miscReg, const MiscReg val,
             ThreadContext *tc);
 
+    RegId
+    flattenRegId(const RegId& regId) const
+    {
+        switch (regId.classValue()) {
+          case IntRegClass:
+            return RegId(IntRegClass, flattenIntIndex(regId.index()));
+          case FloatRegClass:
+            return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+          case CCRegClass:
+            return RegId(CCRegClass, flattenCCIndex(regId.index()));
+          case MiscRegClass:
+            return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+        }
+        return regId;
+    }
+
     int
     flattenIntIndex(int reg) const
     {
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 4a4293e50..b517d462c 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -290,8 +290,8 @@ output decoder {{
             const int MaxLocal = 24;
             const int MaxInput = 32;
             const int MaxMicroReg = 40;
-            RegIndex reg_idx = reg.regIdx;
-            if (reg.regClass == IntRegClass) {
+            RegIndex reg_idx = reg.index();
+            if (reg.isIntReg()) {
                 // If we used a register from the next or previous window,
                 // take out the offset.
                 while (reg_idx >= MaxMicroReg)
@@ -336,7 +336,7 @@ output decoder {{
                         break;
                     }
                 }
-            } else if (reg.regClass == FloatRegClass) {
+            } else if (reg.isFloatReg()) {
                 ccprintf(os, "%%f%d", reg_idx);
             } else {
                 switch (reg_idx) {
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 585dfcced..e60c93cd2 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -155,7 +155,7 @@ output decoder {{
         IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].regIdx == 0) {
+            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
                 ccprintf(os, ", ");
@@ -170,7 +170,7 @@ output decoder {{
                 const SymbolTable *symbab) const
         {
             if (!std::strcmp(mnemonic, "or")) {
-                if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx == 0) {
+                if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
                     if (imm == 0) {
                         printMnemonic(os, "clr");
                     } else {
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 9b3132e40..00e09ce54 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -84,7 +84,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!store ? 0 : 1].regIdx != 0) {
+            if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
                 printSrcReg(response, !store ? 0 : 1);
                 ccprintf(response, " + ");
             }
@@ -111,7 +111,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!save ? 0 : 1].regIdx != 0) {
+            if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
                 printReg(response, _srcRegIdx[!save ? 0 : 1]);
                 ccprintf(response, " + ");
             }
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index f5e1a0826..3f6d35330 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -155,7 +155,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0].regIdx != 0) {
+            if (_srcRegIdx[0].index() != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -175,7 +175,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0].regIdx != 0) {
+            if (_srcRegIdx[0].index() != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh
index 04ec285d4..d326b5dfc 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -66,7 +66,7 @@ namespace X86ISA
                 OpClass __opClass) :
             X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
                     __opClass),
-            src1(_src1.regIdx), src2(_src2.regIdx), dest(_dest.regIdx),
+            src1(_src1.index()), src2(_src2.index()), dest(_dest.index()),
             dataSize(_dataSize), spm(_spm)
         {}
 /*
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index e12a51c4c..1d328d1a1 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -75,12 +75,12 @@ namespace X86ISA
                 Request::FlagsType _memFlags,
                 OpClass __opClass) :
         X86MicroopBase(_machInst, mnem, _instMnem, setFlags, __opClass),
-                scale(_scale), index(_index.regIdx), base(_base.regIdx),
-                disp(_disp), segment(_segment.regIdx),
+                scale(_scale), index(_index.index()), base(_base.index()),
+                disp(_disp), segment(_segment.index()),
                 dataSize(_dataSize), addressSize(_addressSize),
-                memFlags(_memFlags | _segment.regIdx)
+                memFlags(_memFlags | _segment.index())
         {
-            assert(_segment.regIdx < NUM_SEGMENTREGS);
+            assert(_segment.index() < NUM_SEGMENTREGS);
             foldOBit =
                 (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
             foldABit =
@@ -110,7 +110,7 @@ namespace X86ISA
                 _scale, _index, _base, _disp, _segment,
                 _dataSize, _addressSize, _memFlags,
                 __opClass),
-                data(_data.regIdx)
+                data(_data.index())
         {
         }
 
@@ -143,8 +143,8 @@ namespace X86ISA
                 _scale, _index, _base, _disp, _segment,
                 _dataSize, _addressSize, _memFlags,
                 __opClass),
-                dataLow(_dataLow.regIdx),
-                dataHi(_dataHi.regIdx)
+                dataLow(_dataLow.index()),
+                dataHi(_dataHi.index())
         {
         }
 
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index 547780108..5cb0bdbb0 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -59,7 +59,7 @@ namespace X86ISA
                 OpClass __opClass) :
             X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
                     __opClass),
-            src1(_src1.regIdx), dest(_dest.regIdx),
+            src1(_src1.index()), dest(_dest.index()),
             srcSize(_srcSize), destSize(_destSize), ext(_ext)
         {}
 
@@ -102,7 +102,7 @@ namespace X86ISA
             MediaOpBase(_machInst, mnem, _instMnem, setFlags,
                     _src1, _dest, _srcSize, _destSize, _ext,
                     __opClass),
-            src2(_src2.regIdx)
+            src2(_src2.index())
         {}
 
         std::string generateDisassembly(Addr pc,
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index 1accc3555..9838b7cc1 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -64,7 +64,7 @@ namespace X86ISA
                 OpClass __opClass) :
             X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
                     __opClass),
-            src1(_src1.regIdx), dest(_dest.regIdx),
+            src1(_src1.index()), dest(_dest.index()),
             dataSize(_dataSize), ext(_ext)
         {
             foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
@@ -90,7 +90,7 @@ namespace X86ISA
             RegOpBase(_machInst, mnem, _instMnem, setFlags,
                     _src1, _dest, _dataSize, _ext,
                     __opClass),
-            src2(_src2.regIdx)
+            src2(_src2.index())
         {
         }
 
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index b9c5486ed..28c268d4e 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -132,10 +132,9 @@ namespace X86ISA
         static const char * microFormats[9] =
             {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
 
-        RegIndex reg_idx = reg.regIdx;
+        RegIndex reg_idx = reg.index();
 
-        switch (reg.regClass) {
-          case IntRegClass: {
+        if (reg.isIntReg()) {
             const char * suffix = "";
             bool fold = reg_idx & IntFoldBit;
             reg_idx &= ~IntFoldBit;
@@ -198,10 +197,8 @@ namespace X86ISA
                 ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
             }
             ccprintf(os, suffix);
-            break;
-          }
 
-          case FloatRegClass: {
+        } else if (reg.isFloatReg()) {
             if (reg_idx < NumMMXRegs) {
                 ccprintf(os, "%%mmx%d", reg_idx);
                 return;
@@ -219,19 +216,15 @@ namespace X86ISA
             }
             reg_idx -= NumMicroFpRegs;
             ccprintf(os, "%%st(%d)", reg_idx);
-            break;
-          }
 
-          case CCRegClass:
+        } else if (reg.isCCReg()) {
             ccprintf(os, "%%cc%d", reg_idx);
-            break;
 
-          case MiscRegClass:
+        } else if (reg.isMiscReg()) {
             switch (reg_idx) {
               default:
                 ccprintf(os, "%%ctrl%d", reg_idx);
             }
-            break;
         }
     }
 
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 0cea0e132..8dac3ec0f 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -107,7 +107,7 @@ namespace X86ISA
         inline uint64_t merge(uint64_t into, uint64_t val, int size) const
         {
             X86IntReg reg = into;
-            if (_destRegIdx[0].regIdx & IntFoldBit)
+            if (_destRegIdx[0].index() & IntFoldBit)
             {
                 reg.H = val;
                 return reg;
@@ -138,7 +138,7 @@ namespace X86ISA
         {
             X86IntReg reg = from;
             DPRINTF(X86, "Picking with size %d\n", size);
-            if (_srcRegIdx[idx].regIdx & IntFoldBit)
+            if (_srcRegIdx[idx].index() & IntFoldBit)
                 return reg.H;
             switch(size)
             {
@@ -159,7 +159,7 @@ namespace X86ISA
         {
             X86IntReg reg = from;
             DPRINTF(X86, "Picking with size %d\n", size);
-            if (_srcRegIdx[idx].regIdx & IntFoldBit)
+            if (_srcRegIdx[idx].index() & IntFoldBit)
                 return reg.SH;
             switch(size)
             {
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 90ab619cc..099d27c7c 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,6 +38,7 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/registers.hh"
 #include "base/types.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
 class Checkpoint;
@@ -69,6 +70,22 @@ namespace X86ISA
         void setMiscRegNoEffect(int miscReg, MiscReg val);
         void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
 
+        RegId
+        flattenRegId(const RegId& regId) const
+        {
+            switch (regId.classValue()) {
+              case IntRegClass:
+                return RegId(IntRegClass, flattenIntIndex(regId.index()));
+              case FloatRegClass:
+                return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+              case CCRegClass:
+                return RegId(CCRegClass, flattenCCIndex(regId.index()));
+              case MiscRegClass:
+                return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+            }
+            return regId;
+        }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 8a832f5d5..c002a1684 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -95,7 +95,7 @@ def template MicroLimmOpConstructor {{
             InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 setFlags, %(op_class)s),
-                dest(_dest.regIdx), imm(_imm), dataSize(_dataSize)
+                dest(_dest.index()), imm(_imm), dataSize(_dataSize)
     {
         foldOBit = (dataSize == 1 && !machInst.rex.present) ? 1 << 6 : 0;
         %(constructor)s;