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authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
commitaec73ba6af62c8da66fb40e015671541708c1723 (patch)
tree82f2c20a2ec4d48bd73f5445c0775e478f17c67a /src/arch
parent65a5177b53c53b287125cec3f207afeec648d488 (diff)
downloadgem5-aec73ba6af62c8da66fb40e015671541708c1723.tar.xz
ARM: Add a traceflag to print cpsr
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8d547f9c6..ded463267 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -238,6 +238,8 @@ namespace ArmISA
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
CPSR cpsr = val;
+ DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
+ cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
Addr npc = tc->readNextPC() & ~PcModeMask;
if (cpsr.j)
npc = npc | (ULL(1) << PcJBitShift);