Merge zizzer:/bk/newmem

into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : a64362d3cf8de00c97bea25118fee33cffe22707
author: Ali Saidi <saidi@eecs.umich.edu> 2006-07-05 20:30:45 -0400
committer: Ali Saidi <saidi@eecs.umich.edu> 2006-07-05 20:30:45 -0400
commit: b36796914af8bfc6729cc8a519e57572460e43e8 (patch)
tree: 1886edde38b2da28cb45f4e13135b1993502f45d /src/arch
parent: f456360bbcd6e4e4fd1550e96658934affac3eb9 (diff)
parent: 4201ec84b2dd7d96148bf661124dd7b5d0e7204b (diff)
download: gem5-b36796914af8bfc6729cc8a519e57572460e43e8.tar.xz
120 files changed, 4053 insertions, 3062 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 9c193207f..bc517341a 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -25,8 +25,10 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
 
-import os.path
+import os.path, sys
 
 # Import build environment variable from SConstruct.
 Import('env')
@@ -126,13 +128,19 @@ isa_desc_gen_files = Split('decoder.cc decoder.hh')
 isa_desc_gen_files += [CpuModel.dict[cpu].filename
                        for cpu in env['CPU_MODELS']]
 
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+if env['USE_CHECKER']:
+    isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
+
 # The emitter patches up the sources & targets to include the
 # autogenerated files as targets and isa parser itself as a source.
 def isa_desc_emitter(target, source, env):
     return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
 
 # Pieces are in place, so create the builder.
-isa_desc_builder = Builder(action='python2.4 $SOURCES $TARGET.dir $CPU_MODELS',
+python = sys.executable  # use same Python binary used to run scons
+isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
                            emitter = isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
@@ -144,7 +152,6 @@ env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 isa = env['TARGET_ISA'] # someday this may be a list of ISAs
 
 # Let the target architecture define what additional sources it needs
-sources += SConscript(os.path.join(isa, 'SConscript'),
-                      exports = 'env', duplicate = False)
+sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
 
 Return('sources')
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 1b20f8b1f..216c88cc7 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -25,6 +25,9 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+#          Steve Reinhardt
 
 import os
 import sys
diff --git a/src/arch/alpha/aout_machdep.h b/src/arch/alpha/aout_machdep.h
index df9d9ac6a..58991256a 100644
--- a/src/arch/alpha/aout_machdep.h
+++ b/src/arch/alpha/aout_machdep.h
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Nathan Binkert
  */
 
 #ifndef __AOUT_MACHDEP_H__
diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/arguments.cc
index adc371682..9f9002003 100644
--- a/src/arch/alpha/arguments.cc
+++ b/src/arch/alpha/arguments.cc
@@ -24,11 +24,13 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #include "arch/alpha/arguments.hh"
 #include "arch/alpha/vtophys.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/vport.hh"
 
 using namespace AlphaISA;
@@ -54,14 +56,14 @@ AlphaArguments::getArg(bool fp)
 {
     if (number < 6) {
         if (fp)
-            return xc->readFloatRegBits(16 + number);
+            return tc->readFloatRegBits(16 + number);
         else
-            return xc->readIntReg(16 + number);
+            return tc->readIntReg(16 + number);
     } else {
-        Addr sp = xc->readIntReg(30);
-        VirtualPort *vp = xc->getVirtPort(xc);
+        Addr sp = tc->readIntReg(30);
+        VirtualPort *vp = tc->getVirtPort(tc);
         uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t));
-        xc->delVirtPort(vp);
+        tc->delVirtPort(vp);
         return arg;
     }
 }
diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh
index bd1c6cb1d..d977d48d6 100644
--- a/src/arch/alpha/arguments.hh
+++ b/src/arch/alpha/arguments.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_ARGUMENTS_HH__
@@ -35,14 +37,14 @@
 #include "base/refcnt.hh"
 #include "sim/host.hh"
 
-class ExecContext;
+class ThreadContext;
 
 namespace AlphaISA {
 
 class AlphaArguments
 {
   protected:
-    ExecContext *xc;
+    ThreadContext *tc;
     int number;
     uint64_t getArg(bool fp = false);
 
@@ -63,17 +65,17 @@ class AlphaArguments
     RefCountingPtr<Data> data;
 
   public:
-    AlphaArguments(ExecContext *ctx, int n = 0)
-        : xc(ctx), number(n), data(NULL)
+    AlphaArguments(ThreadContext *ctx, int n = 0)
+        : tc(ctx), number(n), data(NULL)
         { assert(number >= 0); data = new Data;}
     AlphaArguments(const AlphaArguments &args)
-        : xc(args.xc), number(args.number), data(args.data) {}
+        : tc(args.tc), number(args.number), data(args.data) {}
     ~AlphaArguments() {}
 
-    ExecContext *getExecContext() const { return xc; }
+    ThreadContext *getThreadContext() const { return tc; }
 
     const AlphaArguments &operator=(const AlphaArguments &args) {
-        xc = args.xc;
+        tc = args.tc;
         number = args.number;
         data = args.data;
         return *this;
@@ -118,7 +120,7 @@ class AlphaArguments
     }
 
     AlphaArguments operator[](int index) {
-        return AlphaArguments(xc, index);
+        return AlphaArguments(tc, index);
     }
 
     template <class T>
@@ -131,13 +133,13 @@ class AlphaArguments
     template <class T>
     operator T *() {
         T *buf = (T *)data->alloc(sizeof(T));
-        CopyData(xc, buf, getArg(), sizeof(T));
+        CopyData(tc, buf, getArg(), sizeof(T));
         return buf;
     }
 
     operator char *() {
         char *buf = data->alloc(2048);
-        CopyStringOut(xc, buf, getArg(), 2048);
+        CopyStringOut(tc, buf, getArg(), 2048);
         return buf;
     }
 };
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 12f7659e6..ae3b668ea 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Nathan Binkert
  */
 
 #include "arch/alpha/tlb.hh"
@@ -34,11 +37,11 @@
 #include "base/stats/events.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
-#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/debug.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
 
 #if FULL_SYSTEM
 
@@ -49,15 +52,19 @@ using namespace EV5;
 //  Machine dependent functions
 //
 void
-AlphaISA::initCPU(ExecContext *xc, int cpuId)
+AlphaISA::initCPU(ThreadContext *tc, int cpuId)
 {
-    initIPRs(xc, cpuId);
+    initIPRs(tc, cpuId);
+
+    tc->setIntReg(16, cpuId);
+    tc->setIntReg(0, cpuId);
 
-    xc->setIntReg(16, cpuId);
-    xc->setIntReg(0, cpuId);
+    AlphaFault *reset = new ResetFault;
 
-    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
-    xc->setNextPC(xc->readPC() + sizeof(MachInst));
+    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
+    tc->setNextPC(tc->readPC() + sizeof(MachInst));
+
+    delete reset;
 }
 
 ////////////////////////////////////////////////////////////////////////
@@ -65,15 +72,15 @@ AlphaISA::initCPU(ExecContext *xc, int cpuId)
 //
 //
 void
-AlphaISA::initIPRs(ExecContext *xc, int cpuId)
+AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
 {
     for (int i = 0; i < NumInternalProcRegs; ++i) {
-        xc->setMiscReg(i, 0);
+        tc->setMiscReg(i, 0);
     }
 
-    xc->setMiscReg(IPR_PAL_BASE, PalBase);
-    xc->setMiscReg(IPR_MCSR, 0x6);
-    xc->setMiscReg(IPR_PALtemp16, cpuId);
+    tc->setMiscReg(IPR_PAL_BASE, PalBase);
+    tc->setMiscReg(IPR_MCSR, 0x6);
+    tc->setMiscReg(IPR_PALtemp16, cpuId);
 }
 
 
@@ -132,12 +139,12 @@ AlphaISA::zeroRegisters(CPU *cpu)
     // Insure ISA semantics
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
-    cpu->cpuXC->setIntReg(ZeroReg, 0);
-    cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
+    cpu->thread->setIntReg(ZeroReg, 0);
+    cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
 Fault
-CPUExecContext::hwrei()
+SimpleThread::hwrei()
 {
     if (!inPalMode())
         return new UnimplementedOpcodeFault;
@@ -145,7 +152,8 @@ CPUExecContext::hwrei()
     setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
-        cpu->kernelStats->hwrei();
+        if (kernelStats)
+            kernelStats->hwrei();
 
         cpu->checkInterrupts = true;
     }
@@ -167,7 +175,7 @@ AlphaISA::MiscRegFile::getDataAsid()
 }
 
 AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
+AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
 {
     uint64_t retval = 0;	// return value, default 0
 
@@ -221,7 +229,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 
       case AlphaISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
-        retval |= xc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
+        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
         break;
 
       case AlphaISA::IPR_VA:
@@ -238,7 +246,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
+            AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -278,11 +286,11 @@ int break_ipl = -1;
 #endif
 
 Fault
-AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
+AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
     uint64_t old;
 
-    if (xc->misspeculating())
+    if (tc->misspeculating())
         return NoFault;
 
     switch (idx) {
@@ -335,7 +343,8 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
-        xc->getCpuPtr()->kernelStats->context(old, val, xc);
+        if (tc->getKernelStats())
+            tc->getKernelStats()->context(old, val, tc);
         break;
 
       case AlphaISA::IPR_DTB_PTE:
@@ -362,14 +371,18 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-        xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
+        if (tc->getKernelStats())
+            tc->getKernelStats()->swpipl(ipr[idx]);
         break;
 
       case AlphaISA::IPR_DTB_CM:
-        if (val & 0x18)
-            xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
-        else
-            xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
+        if (val & 0x18) {
+            if (tc->getKernelStats())
+                tc->getKernelStats()->mode(Kernel::user, tc);
+        } else {
+            if (tc->getKernelStats())
+                tc->getKernelStats()->mode(Kernel::kernel, tc);
+        }
 
       case AlphaISA::IPR_ICM:
         // only write two mode bits - processor mode
@@ -443,21 +456,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // really a control write
         ipr[idx] = 0;
 
-        xc->getDTBPtr()->flushAll();
+        tc->getDTBPtr()->flushAll();
         break;
 
       case AlphaISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        xc->getDTBPtr()->flushProcesses();
+        tc->getDTBPtr()->flushProcesses();
         break;
 
       case AlphaISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        xc->getDTBPtr()->flushAddr(val,
+        tc->getDTBPtr()->flushAddr(val,
                                    DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
         break;
 
@@ -481,7 +494,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          xc->getDTBPtr()->insert(val, pte);
+          tc->getDTBPtr()->insert(val, pte);
       }
         break;
 
@@ -505,7 +518,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+          tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
       }
         break;
 
@@ -513,21 +526,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // really a control write
         ipr[idx] = 0;
 
-        xc->getITBPtr()->flushAll();
+        tc->getITBPtr()->flushAll();
         break;
 
       case AlphaISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        xc->getITBPtr()->flushProcesses();
+        tc->getITBPtr()->flushProcesses();
         break;
 
       case AlphaISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        xc->getITBPtr()->flushAddr(val,
+        tc->getITBPtr()->flushAddr(val,
                                    ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
         break;
 
@@ -541,7 +554,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 }
 
 void
-AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
+AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
 {
     for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
         dest->setMiscReg(i, src->readMiscReg(i));
@@ -553,15 +566,16 @@ AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
  * If return value is false, actual PAL call will be suppressed.
  */
 bool
-CPUExecContext::simPalCheck(int palFunc)
+SimpleThread::simPalCheck(int palFunc)
 {
-    cpu->kernelStats->callpal(palFunc, proxy);
+    if (kernelStats)
+        kernelStats->callpal(palFunc, tc);
 
     switch (palFunc) {
       case PAL::halt:
         halt();
         if (--System::numSystemsRunning == 0)
-            new SimExitEvent("all cpus halted");
+            exitSimLoop("all cpus halted");
         break;
 
       case PAL::bpt:
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index 7c8465cfb..4dd225786 100644
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -24,6 +24,10 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Nathan Binkert
+ *          Ali Saidi
  */
 
 #ifndef __ARCH_ALPHA_EV5_HH__
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 0083aa9f3..eef4361fd 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -24,14 +24,20 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Kevin Lim
  */
 
 #include "arch/alpha/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
 #if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
+#else
+#include "sim/process.hh"
+#include "mem/page_table.hh"
 #endif
 
 namespace AlphaISA
@@ -53,6 +59,12 @@ FaultName ArithmeticFault::_name = "arith";
 FaultVect ArithmeticFault::_vect = 0x0501;
 FaultStat ArithmeticFault::_count;
 
+#if !FULL_SYSTEM
+FaultName PageTableFault::_name = "page_table_fault";
+FaultVect PageTableFault::_vect = 0x0000;
+FaultStat PageTableFault::_count;
+#endif
+
 FaultName InterruptFault::_name = "interrupt";
 FaultVect InterruptFault::_vect = 0x0101;
 FaultStat InterruptFault::_count;
@@ -107,67 +119,91 @@ FaultStat IntegerOverflowFault::_count;
 
 #if FULL_SYSTEM
 
-void AlphaFault::invoke(ExecContext * xc)
+void AlphaFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     countStat()++;
 
     // exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
+    if (setRestartAddress() || !tc->inPalMode())
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
-    xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
-    xc->setNextPC(xc->readPC() + sizeof(MachInst));
+    tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
+    tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
-void DtbFault::invoke(ExecContext * xc)
+void DtbFault::invoke(ThreadContext * tc)
 {
     // Set fault address and flags.  Even though we're modeling an
     // EV5, we use the EV6 technique of not latching fault registers
     // on VPTE loads (instead of locking the registers until IPR_VA is
     // read, like the EV5).  The EV6 approach is cleaner and seems to
     // work with EV5 PAL code, but not the other way around.
-    if (!xc->misspeculating()
+    if (!tc->misspeculating()
         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
         // set VA register with faulting address
-        xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
+        tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
 
         // set MM_STAT register flags
-        xc->setMiscReg(AlphaISA::IPR_MM_STAT,
-            (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
-             | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
+        tc->setMiscReg(AlphaISA::IPR_MM_STAT,
+            (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
+             | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
              | (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
-        xc->setMiscReg(AlphaISA::IPR_VA_FORM,
-            xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+        tc->setMiscReg(AlphaISA::IPR_VA_FORM,
+            tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
     }
 
-    AlphaFault::invoke(xc);
+    AlphaFault::invoke(tc);
 }
 
-void ItbFault::invoke(ExecContext * xc)
+void ItbFault::invoke(ThreadContext * tc)
 {
-    if (!xc->misspeculating()) {
-        xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
-        xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
-                       xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+    if (!tc->misspeculating()) {
+        tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
+        tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
+                       tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
                        (AlphaISA::VAddr(pc).vpn() << 3));
     }
 
-    AlphaFault::invoke(xc);
+    AlphaFault::invoke(tc);
+}
+
+#else //!FULL_SYSTEM
+
+void PageTableFault::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+
+    // address is higher than the stack region or in the current stack region
+    if (vaddr > p->stack_base || vaddr > p->stack_min)
+        FaultBase::invoke(tc);
+
+    // We've accessed the next page
+    if (vaddr > p->stack_min - PageBytes) {
+        warn("Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
+                p->stack_min, p->stack_base, p->stack_min - PageBytes,
+                p->stack_base, vaddr);
+        p->stack_min -= PageBytes;
+        if (p->stack_base - p->stack_min > 8*1024*1024)
+            fatal("Over max stack size for one thread\n");
+        p->pTable->allocate(p->stack_min, PageBytes);
+    } else {
+        FaultBase::invoke(tc);
+    }
 }
 
 #endif
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index e8ccc6b79..11a568174 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Kevin Lim
  */
 
 #ifndef __ALPHA_FAULTS_HH__
@@ -46,7 +49,7 @@ class AlphaFault : public FaultBase
     virtual bool setRestartAddress() {return true;}
   public:
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -78,6 +81,29 @@ class AlignmentFault : public AlphaFault
     bool isAlignmentFault() {return true;}
 };
 
+#if !FULL_SYSTEM
+class PageTableFault : public AlphaFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    PageTableFault(Addr va)
+        : vaddr(va) {}
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+static inline Fault genPageTableFault(Addr va)
+{
+    return new PageTableFault(va);
+}
+#endif
+
 static inline Fault genMachineCheckFault()
 {
     return new MachineCheckFault;
@@ -113,7 +139,7 @@ class ArithmeticFault : public AlphaFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
@@ -147,7 +173,7 @@ class DtbFault : public AlphaFault
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
@@ -248,7 +274,7 @@ class ItbFault : public AlphaFault
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc
index 3e50fb9a5..7cf68e0db 100644
--- a/src/arch/alpha/freebsd/system.cc
+++ b/src/arch/alpha/freebsd/system.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ben Nash
  */
 
 /**
@@ -36,7 +38,7 @@
 #include "arch/alpha/system.hh"
 #include "arch/alpha/freebsd/system.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
 #include "arch/isa_traits.hh"
@@ -70,13 +72,13 @@ FreebsdAlphaSystem::~FreebsdAlphaSystem()
 
 
 void
-FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc)
+FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
 {
     Addr ppc_vaddr = 0;
     Addr timer_vaddr = 0;
 
-    ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1);
-    timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2);
+    ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1);
+    timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2);
 
     virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
     virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
@@ -84,10 +86,10 @@ FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc)
 
 
 void
-FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc)
+FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
 {
-    SkipFuncEvent::process(xc);
-    ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc);
+    SkipFuncEvent::process(tc);
+    ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
 }
 
 
@@ -107,10 +109,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
     Param<uint64_t> system_type;
     Param<uint64_t> system_rev;
 
-    Param<bool> bin;
-    VectorParam<string> binned_fns;
-    Param<bool> bin_int;
-
 END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
@@ -125,10 +123,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
     INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
     INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
     INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
-    INIT_PARAM_DFLT(bin, "is this system to be binned", false),
-    INIT_PARAM(binned_fns, "functions to be broken down and binned"),
-    INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
 
 END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
 
@@ -146,9 +141,6 @@ CREATE_SIM_OBJECT(FreebsdAlphaSystem)
     p->readfile = readfile;
     p->system_type = system_type;
     p->system_rev = system_rev;
-    p->bin = bin;
-    p->binned_fns = binned_fns;
-    p->bin_int = bin_int;
     return new FreebsdAlphaSystem(p);
 }
 
diff --git a/src/arch/alpha/freebsd/system.hh b/src/arch/alpha/freebsd/system.hh
index 5d996955e..e0d874e8f 100644
--- a/src/arch/alpha/freebsd/system.hh
+++ b/src/arch/alpha/freebsd/system.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ben Nash
  */
 
 #ifndef __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
@@ -40,7 +42,7 @@ class FreebsdAlphaSystem : public AlphaSystem
         SkipCalibrateClocksEvent(PCEventQueue *q, const std::string &desc,
                                  Addr addr)
             : SkipFuncEvent(q, desc, addr) {}
-        virtual void process(ExecContext *xc);
+        virtual void process(ThreadContext *tc);
     };
 
     SkipFuncEvent *skipDelayEvent;
@@ -49,7 +51,7 @@ class FreebsdAlphaSystem : public AlphaSystem
   public:
     FreebsdAlphaSystem(Params *p);
     ~FreebsdAlphaSystem();
-    void doCalibrateClocks(ExecContext *xc);
+    void doCalibrateClocks(ThreadContext *tc);
 
 };
 
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index b528df938..7438e7e18 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Control transfer instructions
+//
 
 output header {{
 
@@ -99,7 +106,7 @@ output header {{
         {
         }
 
-        Addr branchTarget(ExecContext *xc) const;
+        Addr branchTarget(ThreadContext *tc) const;
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -114,10 +121,10 @@ output decoder {{
     }
 
     Addr
-    Jump::branchTarget(ExecContext *xc) const
+    Jump::branchTarget(ThreadContext *tc) const
     {
-        Addr NPC = xc->readPC() + 4;
-        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        Addr NPC = tc->readPC() + 4;
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
         return (Rb & ~3) | (NPC & 1);
     }
 
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 1adcfb948..f449d2d69 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// The actual decoder specification
+//
 
 decode OPCODE default Unknown::unknown() {
 
@@ -40,9 +47,11 @@ decode OPCODE default Unknown::unknown() {
         0x23: ldt({{ Fa = Mem.df; }});
         0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
         0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
+#ifdef USE_COPY
         0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
                                       {{ fault = xc->copySrcTranslate(EA); }},
                                       inst_flags = [IsMemRef, IsLoad, IsCopy]);
+#endif
     }
 
     format LoadOrPrefetch {
@@ -62,9 +71,11 @@ decode OPCODE default Unknown::unknown() {
         0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
         0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
         0x27: stt({{ Mem.df = Fa; }});
+#ifdef USE_COPY
         0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
                                        {{ fault = xc->copy(EA); }},
                                        inst_flags = [IsMemRef, IsStore, IsCopy]);
+#endif
     }
 
     format StoreCond {
@@ -73,7 +84,7 @@ decode OPCODE default Unknown::unknown() {
                         uint64_t tmp = write_result;
                         // see stq_c
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED);
+                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
         0x2f: stq_c({{ Mem.uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
@@ -85,7 +96,7 @@ decode OPCODE default Unknown::unknown() {
                         // mailbox access, and we don't update the
                         // result register at all.
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED);
+                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
     }
 
     format IntegerOperate {
@@ -591,8 +602,8 @@ decode OPCODE default Unknown::unknown() {
             0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
             0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
 
-            0x024: mt_fpcr({{ FPCR = Fa.uq; }});
-            0x025: mf_fpcr({{ Fa.uq = FPCR; }});
+            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
+            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
         }
     }
 
@@ -623,7 +634,7 @@ decode OPCODE default Unknown::unknown() {
 #else
                 Ra = curTick;
 #endif
-            }});
+            }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
             // their execute() methods (hence the empty code blocks).
@@ -641,8 +652,8 @@ decode OPCODE default Unknown::unknown() {
             // a barrier on integer and FP traps.  "EXCB is thus a
             // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
             // them the same though.
-            0x0000: trapb({{ }}, IsSerializing, No_OpClass);
-            0x0400: excb({{ }}, IsSerializing, No_OpClass);
+            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
             0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
         }
@@ -652,11 +663,11 @@ decode OPCODE default Unknown::unknown() {
             0xe000: rc({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(0);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(1);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
         format FailUnimpl {
@@ -690,15 +701,15 @@ decode OPCODE default Unknown::unknown() {
     0x00: decode PALFUNC {
         format EmulatedCallPal {
             0x00: halt ({{
-                SimExit(curTick, "halt instruction encountered");
+                exitSimLoop(curTick, "halt instruction encountered");
             }}, IsNonSpeculative);
             0x83: callsys({{
                 xc->syscall(R0);
-            }}, IsNonSpeculative);
+            }}, IsSerializeAfter, IsNonSpeculative);
             // Read uniq reg into ABI return value register (r0)
-            0x9e: rduniq({{ R0 = Runiq; }});
+            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
             // Write uniq reg with value from ABI arg register (r16)
-            0x9f: wruniq({{ Runiq = R16; }});
+            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
         }
     }
 #endif
@@ -735,7 +746,7 @@ decode OPCODE default Unknown::unknown() {
         format HwMoveIPR {
             1: hw_mfpr({{
                 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
-            }});
+            }}, IsIprAccess);
         }
     }
 
@@ -745,69 +756,69 @@ decode OPCODE default Unknown::unknown() {
             1: hw_mtpr({{
                 xc->setMiscRegWithEffect(ipr_index, Ra);
                 if (traceData) { traceData->setData(Ra); }
-            }});
+            }}, IsIprAccess);
         }
     }
 
     format BasicOperate {
         0x1e: decode PALMODE {
             0: OpcdecFault::hw_rei();
-            1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
+            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
         }
 
         // M5 special opcodes use the reserved 0x01 opcode space
         0x01: decode M5FUNC {
             0x00: arm({{
-                AlphaPseudo::arm(xc->xcBase());
+                AlphaPseudo::arm(xc->tcBase());
             }}, IsNonSpeculative);
             0x01: quiesce({{
-                AlphaPseudo::quiesce(xc->xcBase());
-            }}, IsNonSpeculative);
+                AlphaPseudo::quiesce(xc->tcBase());
+            }}, IsNonSpeculative, IsQuiesce);
             0x02: quiesceNs({{
-                AlphaPseudo::quiesceNs(xc->xcBase(), R16);
-            }}, IsNonSpeculative);
+                AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+            }}, IsNonSpeculative, IsQuiesce);
             0x03: quiesceCycles({{
-                AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
-            }}, IsNonSpeculative);
+                AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+            }}, IsNonSpeculative, IsQuiesce);
             0x04: quiesceTime({{
-                R0 = AlphaPseudo::quiesceTime(xc->xcBase());
+                R0 = AlphaPseudo::quiesceTime(xc->tcBase());
             }}, IsNonSpeculative);
             0x10: ivlb({{
-                AlphaPseudo::ivlb(xc->xcBase());
+                AlphaPseudo::ivlb(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x11: ivle({{
-                AlphaPseudo::ivle(xc->xcBase());
+                AlphaPseudo::ivle(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x20: m5exit_old({{
-                AlphaPseudo::m5exit_old(xc->xcBase());
+                AlphaPseudo::m5exit_old(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x21: m5exit({{
-                AlphaPseudo::m5exit(xc->xcBase(), R16);
+                AlphaPseudo::m5exit(xc->tcBase(), R16);
             }}, No_OpClass, IsNonSpeculative);
-            0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
+            0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
             0x40: resetstats({{
-                AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
+                AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x41: dumpstats({{
-                AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
+                AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x42: dumpresetstats({{
-                AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
+                AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x43: m5checkpoint({{
-                AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
+                AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x50: m5readfile({{
-                R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
+                R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
             }}, IsNonSpeculative);
             0x51: m5break({{
-                AlphaPseudo::debugbreak(xc->xcBase());
+                AlphaPseudo::debugbreak(xc->tcBase());
             }}, IsNonSpeculative);
             0x52: m5switchcpu({{
-                AlphaPseudo::switchcpu(xc->xcBase());
+                AlphaPseudo::switchcpu(xc->tcBase());
             }}, IsNonSpeculative);
             0x53: m5addsymbol({{
-                AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
+                AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x54: m5panic({{
                 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index f34c13c42..b4339a1b7 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -25,6 +25,17 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Floating-point instructions
+//
+//	Note that many FP-type instructions which do not support all the
+//	various rounding & trapping modes use the simpler format
+//	BasicOperateWithNopCheck.
+//
 
 output exec {{
     /// Check "FP enabled" machine status bit.  Called when executing any FP
diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa
index 17ecc1a51..45e096ebd 100644
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
 
 output header {{
     /**
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 03a8e1ff5..1270bf8d8 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -25,6 +25,20 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Alpha ISA description file.
+//
+////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
 
 output header {{
 #include <sstream>
@@ -42,7 +56,7 @@ output decoder {{
 #include "base/fenv.hh"
 #include "base/loader/symtab.hh"
 #include "config/ss_compatible_fp.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+#include "cpu/thread_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
 
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 98c7ba979..08a0a2343 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -25,6 +25,14 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+//          Kevin Lim
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory-format instructions: LoadAddress, Load, Store
+//
 
 output header {{
     /**
diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa
index bb2f91e5c..d279ae050 100644
--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Kevin Lim
+
+////////////////////////////////////////////////////////////////////
+//
+// OPCDEC fault instructions
+//
 
 output header {{
     /**
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index e07bea5a8..f4c10da1d 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// PAL calls & PAL-specific instructions
+//
 
 output header {{
     /**
@@ -259,9 +266,11 @@ output decoder {{
     }
 }};
 
-def format HwMoveIPR(code) {{
+def format HwMoveIPR(code, *flags) {{
+    all_flags = ['IprAccessOp']
+    all_flags += flags
     iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
-                        ['IprAccessOp'])
+                        all_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index 392522801..6cfaa6991 100644
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Unimplemented instructions
+//
 
 output header {{
     /**
diff --git a/src/arch/alpha/isa/unknown.isa b/src/arch/alpha/isa/unknown.isa
index 47d166255..1e95ccf68 100644
--- a/src/arch/alpha/isa/unknown.isa
+++ b/src/arch/alpha/isa/unknown.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
 
 output decoder {{
     std::string
diff --git a/src/arch/alpha/isa/util.isa b/src/arch/alpha/isa/util.isa
index 9fbbf6636..8700d1e0b 100644
--- a/src/arch/alpha/isa/util.isa
+++ b/src/arch/alpha/isa/util.isa
@@ -25,6 +25,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Utility functions for execute methods
+//
 
 output exec {{
 
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 65c72115b..663b144ab 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Gabe Black
  */
 
 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
diff --git a/src/arch/alpha/linux/aligned.hh b/src/arch/alpha/linux/aligned.hh
index cabecb283..c4687e348 100644
--- a/src/arch/alpha/linux/aligned.hh
+++ b/src/arch/alpha/linux/aligned.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_LINUX_ALIGNED_HH__
diff --git a/src/arch/alpha/linux/linux.cc b/src/arch/alpha/linux/linux.cc
index f123ae1fe..bc0d48e0d 100644
--- a/src/arch/alpha/linux/linux.cc
+++ b/src/arch/alpha/linux/linux.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #include "arch/alpha/linux/linux.hh"
diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh
index f04e2bfa8..09988bab2 100644
--- a/src/arch/alpha/linux/linux.hh
+++ b/src/arch/alpha/linux/linux.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ALPHA_ALPHA_LINUX_HH
diff --git a/src/arch/alpha/linux/process.cc b/src/arch/alpha/linux/process.cc
index 9f4f65db8..997c78ac9 100644
--- a/src/arch/alpha/linux/process.cc
+++ b/src/arch/alpha/linux/process.cc
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Ali Saidi
  */
 
 #include "arch/alpha/linux/linux.hh"
@@ -31,7 +34,7 @@
 #include "arch/alpha/isa_traits.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"
 
 #include "sim/process.hh"
@@ -45,9 +48,9 @@ using namespace AlphaISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -55,7 +58,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
     return 0;
 }
 
@@ -64,18 +67,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
 /// different in practice from those used by Tru64 processes.
 static SyscallReturn
 osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 45: { // GSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(xc->getMemPort());
+          fpcr.copyOut(tc->getMemPort());
           return 0;
       }
 
@@ -91,17 +94,17 @@ osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
 /// Target osf_setsysinfo() handler.
 static SyscallReturn
 osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 14: { // SSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(xc->getMemPort());
+          fpcr.copyIn(tc->getMemPort());
           DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
diff --git a/src/arch/alpha/linux/process.hh b/src/arch/alpha/linux/process.hh
index 2e0566665..9cc7dc7b6 100644
--- a/src/arch/alpha/linux/process.hh
+++ b/src/arch/alpha/linux/process.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
  */
 
 #ifndef __ALPHA_LINUX_PROCESS_HH__
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index cdb96096c..9fe63c390 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -24,6 +24,11 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Lisa Hsu
+ *          Nathan Binkert
+ *          Steve Reinhardt
  */
 
 /**
@@ -41,7 +46,7 @@
 #include "arch/alpha/linux/threadinfo.hh"
 #include "arch/alpha/system.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "dev/platform.hh"
 #include "kern/linux/printk.hh"
@@ -132,24 +137,6 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p)
     } else {
         printThreadEvent = NULL;
     }
-
-    if (params()->bin_int) {
-        intStartEvent = addPalFuncEvent<InterruptStartEvent>("sys_int_21");
-        if (!intStartEvent)
-            panic("could not find symbol: sys_int_21\n");
-
-        intEndEvent = addPalFuncEvent<InterruptEndEvent>("rti_to_kern");
-        if (!intEndEvent)
-            panic("could not find symbol: rti_to_kern\n");
-
-        intEndEvent2 = addPalFuncEvent<InterruptEndEvent>("rti_to_user");
-        if (!intEndEvent2)
-            panic("could not find symbol: rti_to_user\n");
-
-        intEndEvent3 = addKernelFuncEvent<InterruptEndEvent>("do_softirq");
-        if (!intEndEvent3)
-            panic("could not find symbol: do_softirq\n");
-    }
 }
 
 LinuxAlphaSystem::~LinuxAlphaSystem()
@@ -163,37 +150,37 @@ LinuxAlphaSystem::~LinuxAlphaSystem()
     delete debugPrintkEvent;
     delete idleStartEvent;
     delete printThreadEvent;
-    delete intStartEvent;
-    delete intEndEvent;
-    delete intEndEvent2;
 }
 
 
 void
-LinuxAlphaSystem::setDelayLoop(ExecContext *xc)
+LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
 {
     Addr addr = 0;
     if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
-        Tick cpuFreq = xc->getCpuPtr()->frequency();
+        Tick cpuFreq = tc->getCpuPtr()->frequency();
         Tick intrFreq = platform->intrFrequency();
-        xc->getVirtPort(xc)->write(addr,
-                (uint32_t)((cpuFreq / intrFreq) * 0.9988));
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
+        tc->delVirtPort(vp);
     }
 }
 
 
 void
-LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc)
+LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc)
 {
-    SkipFuncEvent::process(xc);
+    SkipFuncEvent::process(tc);
     // calculate and set loops_per_jiffy
-    ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc);
+    ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc);
 }
 
 void
-LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc)
+LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
 {
-    Linux::ThreadInfo ti(xc);
+    Linux::ThreadInfo ti(tc);
 
     DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n",
             ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
@@ -216,10 +203,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
     Param<uint64_t> system_type;
     Param<uint64_t> system_rev;
 
-    Param<bool> bin;
-    VectorParam<string> binned_fns;
-    Param<bool> bin_int;
-
 END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
@@ -234,10 +217,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
     INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
     INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
     INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
-    INIT_PARAM_DFLT(bin, "is this system to be binned", false),
-    INIT_PARAM(binned_fns, "functions to be broken down and binned"),
-    INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
 
 END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
 
@@ -255,9 +235,6 @@ CREATE_SIM_OBJECT(LinuxAlphaSystem)
     p->readfile = readfile;
     p->system_type = system_type;
     p->system_rev = system_rev;
-    p->bin = bin;
-    p->binned_fns = binned_fns;
-    p->bin_int = bin_int;
     return new LinuxAlphaSystem(p);
 }
 
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 0c1fb037e..6921ba820 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -24,12 +24,16 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Lisa Hsu
+ *          Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__
 #define __ARCH_ALPHA_LINUX_SYSTEM_HH__
 
-class ExecContext;
+class ThreadContext;
 
 class BreakPCEvent;
 class IdleStartEvent;
@@ -41,7 +45,7 @@ using namespace AlphaISA;
 using namespace Linux;
 
 /**
- * This class contains linux specific system code (Loading, Events, Binning).
+ * This class contains linux specific system code (Loading, Events).
  * It points to objects that are the system binaries to load and patches them
  * appropriately to work in simulator.
  */
@@ -53,7 +57,7 @@ class LinuxAlphaSystem : public AlphaSystem
       public:
         SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr)
             : SkipFuncEvent(q, desc, addr) {}
-        virtual void process(ExecContext *xc);
+        virtual void process(ThreadContext *tc);
     };
 
     class PrintThreadInfo : public PCEvent
@@ -61,7 +65,7 @@ class LinuxAlphaSystem : public AlphaSystem
       public:
         PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr)
             : PCEvent(q, desc, addr) {}
-        virtual void process(ExecContext *xc);
+        virtual void process(ThreadContext *tc);
     };
 
 
@@ -120,18 +124,6 @@ class LinuxAlphaSystem : public AlphaSystem
      */
     PrintThreadInfo *printThreadEvent;
 
-    /**
-     * Event to bin Interrupts seperately from kernel code
-     */
-    InterruptStartEvent *intStartEvent;
-
-    /**
-     * Event to bin Interrupts seperately from kernel code
-     */
-    InterruptEndEvent *intEndEvent;
-    InterruptEndEvent *intEndEvent2;
-    InterruptEndEvent *intEndEvent3;
-
     /** Grab the PCBB of the idle process when it starts */
     IdleStartEvent *idleStartEvent;
 
@@ -139,7 +131,7 @@ class LinuxAlphaSystem : public AlphaSystem
     LinuxAlphaSystem(Params *p);
     ~LinuxAlphaSystem();
 
-    void setDelayLoop(ExecContext *xc);
+    void setDelayLoop(ThreadContext *tc);
 };
 
 #endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__
diff --git a/src/arch/alpha/linux/thread_info.hh b/src/arch/alpha/linux/thread_info.hh
index 88791b00d..78257da56 100644
--- a/src/arch/alpha/linux/thread_info.hh
+++ b/src/arch/alpha/linux/thread_info.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_LINUX_THREAD_INFO_H__
diff --git a/src/arch/alpha/linux/threadinfo.hh b/src/arch/alpha/linux/threadinfo.hh
index 8f03c9314..caeb69f15 100644
--- a/src/arch/alpha/linux/threadinfo.hh
+++ b/src/arch/alpha/linux/threadinfo.hh
@@ -24,13 +24,16 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__
 #define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__
 
 #include "arch/alpha/linux/thread_info.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/sched.hh"
 #include "sim/vptr.hh"
 
@@ -39,10 +42,10 @@ namespace Linux {
 class ThreadInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
   public:
-    ThreadInfo(ExecContext *exec) : xc(exec) {}
+    ThreadInfo(ThreadContext *_tc) : tc(_tc) {}
     ~ThreadInfo() {}
 
     inline VPtr<thread_info>
@@ -54,15 +57,15 @@ class ThreadInfo
          * thread_info struct. So we can get the address by masking off
          * the lower 14 bits.
          */
-        current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
-        return VPtr<thread_info>(xc, current);
+        current = tc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
+        return VPtr<thread_info>(tc, current);
     }
 
     inline VPtr<task_struct>
     curTaskInfo()
     {
         Addr task = curThreadInfo()->task;
-        return VPtr<task_struct>(xc, task);
+        return VPtr<task_struct>(tc, task);
     }
 
     std::string
diff --git a/src/arch/alpha/osfpal.cc b/src/arch/alpha/osfpal.cc
index a48bd28d9..ed1d255a6 100644
--- a/src/arch/alpha/osfpal.cc
+++ b/src/arch/alpha/osfpal.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #include "arch/alpha/osfpal.hh"
diff --git a/src/arch/alpha/osfpal.hh b/src/arch/alpha/osfpal.hh
index f46d2bce1..cf3940b85 100644
--- a/src/arch/alpha/osfpal.hh
+++ b/src/arch/alpha/osfpal.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #ifndef __OSFPAL_HH__
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 25ee79692..970292cd8 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -24,59 +24,22 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #include "arch/alpha/constants.hh"
 #include "arch/alpha/process.hh"
-#include "arch/alpha/linux/process.hh"
-#include "arch/alpha/tru64/process.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
-#include "cpu/exec_context.hh"
-#include "sim/builder.hh"
+#include "cpu/thread_context.hh"
 #include "sim/system.hh"
 
 
 using namespace AlphaISA;
 using namespace std;
 
-AlphaLiveProcess *
-AlphaLiveProcess::create(const std::string &nm, System *system, int stdin_fd,
-        int stdout_fd, int stderr_fd, std::string executable,
-        std::vector<std::string> &argv, std::vector<std::string> &envp)
-{
-    AlphaLiveProcess *process = NULL;
-
-    ObjectFile *objFile = createObjectFile(executable);
-    if (objFile == NULL) {
-        fatal("Can't load object file %s", executable);
-    }
-
-
-    if (objFile->getArch() != ObjectFile::Alpha)
-        fatal("Object file does not match architecture.");
-    switch (objFile->getOpSys()) {
-      case ObjectFile::Tru64:
-        process = new AlphaTru64Process(nm, objFile, system,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-
-      case ObjectFile::Linux:
-        process = new AlphaLinuxProcess(nm, objFile, system,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-
-      default:
-        fatal("Unknown/unsupported operating system.");
-    }
-
-    if (process == NULL)
-        fatal("Unknown error creating process object.");
-    return process;
-}
-
 AlphaLiveProcess::AlphaLiveProcess(const std::string &nm, ObjectFile *objFile,
         System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
         std::vector<std::string> &argv, std::vector<std::string> &envp)
@@ -104,64 +67,7 @@ AlphaLiveProcess::startup()
 {
     argsInit(MachineBytes, VMPageSize);
 
-    execContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
+    threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
 }
 
 
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaLiveProcess)
-
-    VectorParam<string> cmd;
-    Param<string> executable;
-    Param<string> input;
-    Param<string> output;
-    VectorParam<string> env;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaLiveProcess)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaLiveProcess)
-
-    INIT_PARAM(cmd, "command line (executable plus arguments)"),
-    INIT_PARAM(executable, "executable (overrides cmd[0] if set)"),
-    INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"),
-    INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"),
-    INIT_PARAM(env, "environment settings"),
-    INIT_PARAM(system, "system")
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaLiveProcess)
-
-
-CREATE_SIM_OBJECT(AlphaLiveProcess)
-{
-    string in = input;
-    string out = output;
-
-    // initialize file descriptors to default: same as simulator
-    int stdin_fd, stdout_fd, stderr_fd;
-
-    if (in == "stdin" || in == "cin")
-        stdin_fd = STDIN_FILENO;
-    else
-        stdin_fd = Process::openInputFile(input);
-
-    if (out == "stdout" || out == "cout")
-        stdout_fd = STDOUT_FILENO;
-    else if (out == "stderr" || out == "cerr")
-        stdout_fd = STDERR_FILENO;
-    else
-        stdout_fd = Process::openOutputFile(out);
-
-    stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO;
-
-    return AlphaLiveProcess::create(getInstanceName(), system,
-                               stdin_fd, stdout_fd, stderr_fd,
-                               (string)executable == "" ? cmd[0] : executable,
-                               cmd, env);
-}
-
-
-REGISTER_SIM_OBJECT("AlphaLiveProcess", AlphaLiveProcess)
-
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index d97b36e2d..5d5c9a52e 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #ifndef __ALPHA_PROCESS_HH__
@@ -46,18 +49,6 @@ class AlphaLiveProcess : public LiveProcess
                 std::vector<std::string> &envp);
 
     void startup();
-
-  public:
-    // this function is used to create the LiveProcess object, since
-    // we can't tell which subclass of LiveProcess to use until we
-    // open and look at the object file.
-    static AlphaLiveProcess *create(const std::string &nm,
-                               System *_system,
-                               int stdin_fd, int stdout_fd, int stderr_fd,
-                               std::string executable,
-                               std::vector<std::string> &argv,
-                               std::vector<std::string> &envp);
-
 };
 
 
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index af01b7829..1025412cd 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
  */
 
 #ifndef __ARCH_ALPHA_REGFILE_HH__
@@ -34,7 +36,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 
 namespace AlphaISA
 {
@@ -60,6 +62,8 @@ namespace AlphaISA
 
         void unserialize(Checkpoint *cp, const std::string &section);
 
+        void clear()
+        { bzero(regs, sizeof(regs)); }
     };
 
     class FloatRegFile
@@ -75,6 +79,8 @@ namespace AlphaISA
 
         void unserialize(Checkpoint *cp, const std::string &section);
 
+        void clear()
+        { bzero(d, sizeof(d)); }
     };
 
     class MiscRegFile {
@@ -88,7 +94,7 @@ namespace AlphaISA
         MiscReg readReg(int misc_reg);
 
         MiscReg readRegWithEffect(int misc_reg, Fault &fault,
-                ExecContext *xc);
+                ThreadContext *tc);
 
         //These functions should be removed once the simplescalar cpu model
         //has been replaced.
@@ -98,8 +104,14 @@ namespace AlphaISA
         Fault setReg(int misc_reg, const MiscReg &val);
 
         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                ExecContext *xc);
+                ThreadContext *tc);
 
+        void clear()
+        {
+            fpcr = uniq = 0;
+            lock_flag = 0;
+            lock_addr = 0;
+        }
 #if FULL_SYSTEM
       protected:
         typedef uint64_t InternalProcReg;
@@ -107,9 +119,9 @@ namespace AlphaISA
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
       private:
-        InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
+        InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
 
-        Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
+        Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
 #endif
         friend class RegFile;
     };
@@ -169,9 +181,9 @@ namespace AlphaISA
 
         void clear()
         {
-            bzero(&intRegFile, sizeof(intRegFile));
-            bzero(&floatRegFile, sizeof(floatRegFile));
-            bzero(&miscRegFile, sizeof(miscRegFile));
+            intRegFile.clear();
+            floatRegFile.clear();
+            miscRegFile.clear();
         }
 
         MiscReg readMiscReg(int miscReg)
@@ -180,10 +192,10 @@ namespace AlphaISA
         }
 
         MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ExecContext *xc)
+                Fault &fault, ThreadContext *tc)
         {
             fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
         }
 
         Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -192,9 +204,9 @@ namespace AlphaISA
         }
 
         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc)
+                ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+            return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
@@ -266,12 +278,12 @@ namespace AlphaISA
         }
     };
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
 #if FULL_SYSTEM
-    void copyIprs(ExecContext *src, ExecContext *dest);
+    void copyIprs(ThreadContext *src, ThreadContext *dest);
 #endif
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index 8691e12dc..d70a4d6dd 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #include <string>
@@ -34,36 +36,42 @@
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace AlphaISA;
 
-ProcessInfo::ProcessInfo(ExecContext *_xc)
-    : xc(_xc)
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+    : tc(_tc)
 {
     Addr addr = 0;
 
-    if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+
+    if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
         panic("thread info not compiled into kernel\n");
-    thread_info_size = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+    thread_info_size = vp->readGtoH<int32_t>(addr);
 
-    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+    if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
         panic("thread info not compiled into kernel\n");
-    task_struct_size = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+    task_struct_size = vp->readGtoH<int32_t>(addr);
 
-    if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+    if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
         panic("thread info not compiled into kernel\n");
-    task_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+    task_off = vp->readGtoH<int32_t>(addr);
 
-    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+    if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
         panic("thread info not compiled into kernel\n");
-    pid_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+    pid_off = vp->readGtoH<int32_t>(addr);
 
-    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+    if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
         panic("thread info not compiled into kernel\n");
-    name_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+    name_off = vp->readGtoH<int32_t>(addr);
+
+    tc->delVirtPort(vp);
 }
 
 Addr
@@ -73,7 +81,15 @@ ProcessInfo::task(Addr ksp) const
     if (base == ULL(0xfffffc0000000000))
         return 0;
 
-    return gtoh(xc->getVirtPort()->read<Addr>(base + task_off));
+    Addr tsk;
+
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+    tsk = vp->readGtoH<Addr>(base + task_off);
+    tc->delVirtPort(vp);
+
+    return tsk;
 }
 
 int
@@ -83,7 +99,15 @@ ProcessInfo::pid(Addr ksp) const
     if (!task)
         return -1;
 
-    return gtoh(xc->getVirtPort()->read<uint16_t>(task + pid_off));
+    uint16_t pd;
+
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+    pd = vp->readGtoH<uint16_t>(task + pid_off);
+    tc->delVirtPort(vp);
+
+    return pd;
 }
 
 string
@@ -94,7 +118,7 @@ ProcessInfo::name(Addr ksp) const
         return "console";
 
     char comm[256];
-    CopyStringOut(xc, comm, task + name_off, sizeof(comm));
+    CopyStringOut(tc, comm, task + name_off, sizeof(comm));
     if (!comm[0])
         return "startup";
 
@@ -102,14 +126,14 @@ ProcessInfo::name(Addr ksp) const
 }
 
 StackTrace::StackTrace()
-    : xc(0), stack(64)
+    : tc(0), stack(64)
 {
 }
 
-StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
-    : xc(0), stack(64)
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+    : tc(0), stack(64)
 {
-    trace(_xc, inst);
+    trace(_tc, inst);
 }
 
 StackTrace::~StackTrace()
@@ -117,15 +141,15 @@ StackTrace::~StackTrace()
 }
 
 void
-StackTrace::trace(ExecContext *_xc, bool is_call)
+StackTrace::trace(ThreadContext *_tc, bool is_call)
 {
-    xc = _xc;
+    tc = _tc;
 
-    bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+    bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
-    Addr pc = xc->readNextPC();
-    bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
-        pc <= xc->getSystemPtr()->kernelEnd;
+    Addr pc = tc->readNextPC();
+    bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+        pc <= tc->getSystemPtr()->kernelEnd;
 
     if (usermode) {
         stack.push_back(user);
@@ -137,8 +161,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
         return;
     }
 
-    SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
-    Addr ksp = xc->readIntReg(TheISA::StackPointerReg);
+    SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+    Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
     Addr bottom = ksp & ~0x3fff;
     Addr addr;
 
@@ -147,7 +171,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
             panic("could not find address %#x", pc);
 
         stack.push_back(addr);
-        pc = xc->readPC();
+        pc = tc->readPC();
     }
 
     Addr ra;
@@ -179,8 +203,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
             return;
         }
 
-        bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
-            pc <= xc->getSystemPtr()->kernelEnd;
+        bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+            pc <= tc->getSystemPtr()->kernelEnd;
         if (!kernel)
             return;
 
@@ -194,22 +218,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
 bool
 StackTrace::isEntry(Addr addr)
 {
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
         return true;
 
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
         return true;
 
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
         return true;
 
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
         return true;
 
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
         return true;
 
-    if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
+    if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
         return true;
 
     return false;
@@ -294,7 +318,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
 
     for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
         MachInst inst;
-        CopyOut(xc, (uint8_t *)&inst, pc, sizeof(MachInst));
+        CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
 
         int reg, disp;
         if (decodeStack(inst, disp)) {
@@ -305,7 +329,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
             size += disp;
         } else if (decodeSave(inst, reg, disp)) {
             if (!ra && reg == ReturnAddressReg) {
-                CopyOut(xc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+                CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
                 if (!ra) {
                     // panic("no return address value pc=%#x\n", pc);
                     return false;
@@ -321,8 +345,8 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
 void
 StackTrace::dump()
 {
-    StringWrap name(xc->getCpuPtr()->name());
-    SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
+    StringWrap name(tc->getCpuPtr()->name());
+    SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
 
     DPRINTFN("------ Stack ------\n");
 
diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh
index 1d8d97a79..d12aee211 100644
--- a/src/arch/alpha/stacktrace.hh
+++ b/src/arch/alpha/stacktrace.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_STACKTRACE_HH__
@@ -32,13 +34,13 @@
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
-class ExecContext;
+class ThreadContext;
 class StackTrace;
 
 class ProcessInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
     int thread_info_size;
     int task_struct_size;
@@ -47,7 +49,7 @@ class ProcessInfo
     int name_off;
 
   public:
-    ProcessInfo(ExecContext *_xc);
+    ProcessInfo(ThreadContext *_tc);
 
     Addr task(Addr ksp) const;
     int pid(Addr ksp) const;
@@ -59,7 +61,7 @@ class StackTrace
   protected:
     typedef TheISA::MachInst MachInst;
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
     std::vector<Addr> stack;
 
   private:
@@ -68,21 +70,21 @@ class StackTrace
     bool decodeSave(MachInst inst, int &reg, int &disp);
     bool decodeStack(MachInst inst, int &disp);
 
-    void trace(ExecContext *xc, bool is_call);
+    void trace(ThreadContext *tc, bool is_call);
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
+    StackTrace(ThreadContext *tc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
     {
-        xc = 0;
+        tc = 0;
         stack.clear();
     }
 
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
+    bool valid() const { return tc != NULL; }
+    bool trace(ThreadContext *tc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -104,7 +106,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
@@ -112,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
     if (valid())
         clear();
 
-    trace(xc, !inst->isReturn());
+    trace(tc, !inst->isReturn());
     return true;
 }
 
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 4234019cd..dce7365aa 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  */
 
 #include "arch/alpha/ev5.hh"
@@ -230,10 +233,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
     Param<uint64_t> system_type;
     Param<uint64_t> system_rev;
 
-    Param<bool> bin;
-    VectorParam<std::string> binned_fns;
-    Param<bool> bin_int;
-
 END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
@@ -248,10 +247,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
     INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
     INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
     INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
-    INIT_PARAM_DFLT(bin, "is this system to be binned", false),
-    INIT_PARAM(binned_fns, "functions to be broken down and binned"),
-    INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
 
 END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
 
@@ -269,9 +265,6 @@ CREATE_SIM_OBJECT(AlphaSystem)
     p->readfile = readfile;
     p->system_type = system_type;
     p->system_rev = system_rev;
-    p->bin = bin;
-    p->binned_fns = binned_fns;
-    p->bin_int = bin_int;
     return new AlphaSystem(p);
 }
 
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 924e16826..0f4f64581 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_SYSTEM_HH__
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 05b02d74b..c6684274b 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -24,6 +24,10 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Andrew Schultz
  */
 
 #include <string>
@@ -34,7 +38,7 @@
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "config/alpha_tlaser.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "sim/builder.hh"
 
 using namespace std;
@@ -282,7 +286,7 @@ AlphaITB::regStats()
 
 
 Fault
-AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
+AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
 {
     if (AlphaISA::PcPAL(req->getVaddr())) {
         // strip off PAL PC marker (lsb is 1)
@@ -304,13 +308,13 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
 #if ALPHA_TLASER
-        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2) {
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
 #endif
             // only valid in kernel mode
-            if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
+            if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
                 AlphaISA::mode_kernel) {
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -328,7 +332,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
 
         } else {
             // not a physical address: need to look up pte
-            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
             AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
                                         asn);
 
@@ -343,7 +347,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
 
             // check permissions for this access
             if (!(pte->xre &
-                  (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
+                  (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
                 // instruction access fault
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -439,12 +443,12 @@ AlphaDTB::regStats()
 }
 
 Fault
-AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
+AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
 {
-    Addr pc = xc->readPC();
+    Addr pc = tc->readPC();
 
     AlphaISA::mode_type mode =
-        (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
+        (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
 
 
     /**
@@ -460,7 +464,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
     if (pc & 0x1) {
         mode = (req->getFlags() & ALTMODE) ?
             (AlphaISA::mode_type)ALT_MODE_AM(
-                xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
+                tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
             : AlphaISA::mode_kernel;
     }
 
@@ -478,14 +482,14 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
 
         // Check for "superpage" mapping
 #if ALPHA_TLASER
-        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2) {
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
 #endif
 
             // only valid in kernel mode
-            if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
+            if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
                 AlphaISA::mode_kernel) {
                 if (write) { write_acv++; } else { read_acv++; }
                 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
@@ -509,7 +513,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
             else
                 read_accesses++;
 
-            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
 
             // not a physical address: need to look up pte
             AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index f6256020e..07d01fa5c 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
  */
 
 #ifndef __ALPHA_MEMORY_HH__
@@ -38,7 +41,7 @@
 #include "mem/request.hh"
 #include "sim/sim_object.hh"
 
-class ExecContext;
+class ThreadContext;
 
 class AlphaTLB : public SimObject
 {
@@ -92,7 +95,7 @@ class AlphaITB : public AlphaTLB
     AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(RequestPtr &req, ExecContext *xc) const;
+    Fault translate(RequestPtr &req, ThreadContext *tc) const;
 };
 
 class AlphaDTB : public AlphaTLB
@@ -115,7 +118,7 @@ class AlphaDTB : public AlphaTLB
     AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(RequestPtr &req, ExecContext *xc, bool write) const;
+    Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__
diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc
index 55f75f7d0..82e44b9e7 100644
--- a/src/arch/alpha/tru64/process.cc
+++ b/src/arch/alpha/tru64/process.cc
@@ -24,13 +24,16 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Ali Saidi
  */
 
 #include "arch/alpha/tru64/tru64.hh"
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/tru64/process.hh"
 
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/tru64/tru64.hh"
 
 #include "sim/process.hh"
@@ -42,9 +45,9 @@ using namespace AlphaISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<AlphaTru64::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<AlphaTru64::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "OSF1");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -52,43 +55,43 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "732");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
     return 0;
 }
 
 /// Target getsysyinfo() handler.
 static SyscallReturn
 getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-               ExecContext *xc)
+               ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case AlphaTru64::GSI_MAX_CPU: {
-          TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1));
+          TypedBufferArg<uint32_t> max_cpu(tc->getSyscallArg(1));
           *max_cpu = htog((uint32_t)process->numCpus());
-          max_cpu.copyOut(xc->getMemPort());
+          max_cpu.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_CPUS_IN_BOX: {
-          TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1));
+          TypedBufferArg<uint32_t> cpus_in_box(tc->getSyscallArg(1));
           *cpus_in_box = htog((uint32_t)process->numCpus());
-          cpus_in_box.copyOut(xc->getMemPort());
+          cpus_in_box.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_PHYSMEM: {
-          TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> physmem(tc->getSyscallArg(1));
           *physmem = htog((uint64_t)1024 * 1024);	// physical memory in KB
-          physmem.copyOut(xc->getMemPort());
+          physmem.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_CPU_INFO: {
-          TypedBufferArg<AlphaTru64::cpu_info> infop(xc->getSyscallArg(1));
+          TypedBufferArg<AlphaTru64::cpu_info> infop(tc->getSyscallArg(1));
 
           infop->current_cpu = htog(0);
           infop->cpus_in_box = htog(process->numCpus());
@@ -100,30 +103,30 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
           infop->cpu_ex_binding = htog(0);
           infop->mhz = htog(667);
 
-          infop.copyOut(xc->getMemPort());
+          infop.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_PROC_TYPE: {
-          TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> proc_type(tc->getSyscallArg(1));
           *proc_type = htog((uint64_t)11);
-          proc_type.copyOut(xc->getMemPort());
+          proc_type.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_PLATFORM_NAME: {
-          BufferArg bufArg(xc->getSyscallArg(1), nbytes);
+          BufferArg bufArg(tc->getSyscallArg(1), nbytes);
           strncpy((char *)bufArg.bufferPtr(),
                   "COMPAQ Professional Workstation XP1000",
                   nbytes);
-          bufArg.copyOut(xc->getMemPort());
+          bufArg.copyOut(tc->getMemPort());
           return 1;
       }
 
       case AlphaTru64::GSI_CLK_TCK: {
-          TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> clk_hz(tc->getSyscallArg(1));
           *clk_hz = htog((uint64_t)1024);
-          clk_hz.copyOut(xc->getMemPort());
+          clk_hz.copyOut(tc->getMemPort());
           return 1;
       }
 
@@ -138,14 +141,14 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
 /// Target setsysyinfo() handler.
 static SyscallReturn
 setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-               ExecContext *xc)
+               ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
+    unsigned op = tc->getSyscallArg(0);
 
     switch (op) {
       case AlphaTru64::SSI_IEEE_FP_CONTROL:
         warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n",
-             xc->getSyscallArg(1));
+             tc->getSyscallArg(1));
         break;
 
       default:
@@ -160,22 +163,22 @@ setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
 /// Target table() handler.
 static
 SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process,
-                        ExecContext *xc)
+                        ThreadContext *tc)
 {
     using namespace std;
     using namespace TheISA;
 
-    int id = xc->getSyscallArg(0);		// table ID
-    int index = xc->getSyscallArg(1);	// index into table
+    int id = tc->getSyscallArg(0);		// table ID
+    int index = tc->getSyscallArg(1);	// index into table
     // arg 2 is buffer pointer; type depends on table ID
-    int nel = xc->getSyscallArg(3);		// number of elements
-    int lel = xc->getSyscallArg(4);		// expected element size
+    int nel = tc->getSyscallArg(3);		// number of elements
+    int lel = tc->getSyscallArg(4);		// expected element size
 
     switch (id) {
       case AlphaTru64::TBL_SYSINFO: {
           if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo))
               return -EINVAL;
-          TypedBufferArg<Tru64::tbl_sysinfo> elp(xc->getSyscallArg(2));
+          TypedBufferArg<Tru64::tbl_sysinfo> elp(tc->getSyscallArg(2));
 
           const int clk_hz = one_million;
           elp->si_user = htog(curTick / (Clock::Frequency / clk_hz));
@@ -187,7 +190,7 @@ SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process,
           elp->si_phz = htog(clk_hz);
           elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch?
           elp->si_max_procs = htog(process->numCpus());
-          elp.copyOut(xc->getMemPort());
+          elp.copyOut(tc->getMemPort());
           return 0;
       }
 
diff --git a/src/arch/alpha/tru64/process.hh b/src/arch/alpha/tru64/process.hh
index 1cde4cac0..5d91f6ac1 100644
--- a/src/arch/alpha/tru64/process.hh
+++ b/src/arch/alpha/tru64/process.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
  */
 
 #ifndef __ALPHA_TRU64_PROCESS_HH__
diff --git a/src/arch/alpha/tru64/system.cc b/src/arch/alpha/tru64/system.cc
index 2ad06d679..6c0edc1ee 100644
--- a/src/arch/alpha/tru64/system.cc
+++ b/src/arch/alpha/tru64/system.cc
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Lisa Hsu
  */
 
 #include "arch/alpha/tru64/system.hh"
@@ -32,7 +35,7 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/tru64/tru64_events.hh"
 #include "kern/system_events.hh"
 #include "mem/physical.hh"
@@ -104,9 +107,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
     Param<uint64_t> system_type;
     Param<uint64_t> system_rev;
 
-    Param<bool> bin;
-    VectorParam<string> binned_fns;
-
 END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
@@ -121,9 +121,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
     INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
     INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
     INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1),
-    INIT_PARAM_DFLT(bin, "is this system to be binned", false),
-    INIT_PARAM(binned_fns, "functions to be broken down and binned")
+    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1)
 
 END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
 
@@ -141,9 +139,6 @@ CREATE_SIM_OBJECT(Tru64AlphaSystem)
     p->readfile = readfile;
     p->system_type = system_type;
     p->system_rev = system_rev;
-    p->bin = bin;
-    p->binned_fns = binned_fns;
-    p->bin_int = false;
 
     return new Tru64AlphaSystem(p);
 }
diff --git a/src/arch/alpha/tru64/system.hh b/src/arch/alpha/tru64/system.hh
index 0e0cc1bc8..947e92f50 100644
--- a/src/arch/alpha/tru64/system.hh
+++ b/src/arch/alpha/tru64/system.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Lisa Hsu
  */
 
 #ifndef __ARCH_ALPHA_TRU64_SYSTEM_HH__
@@ -33,7 +36,7 @@
 #include "arch/isa_traits.hh"
 #include "sim/system.hh"
 
-class ExecContext;
+class ThreadContext;
 
 class BreakPCEvent;
 class BadAddrEvent;
diff --git a/src/arch/alpha/tru64/tru64.cc b/src/arch/alpha/tru64/tru64.cc
index 4a3e653c1..56b04846f 100644
--- a/src/arch/alpha/tru64/tru64.cc
+++ b/src/arch/alpha/tru64/tru64.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #include "arch/alpha/tru64/tru64.hh"
diff --git a/src/arch/alpha/tru64/tru64.hh b/src/arch/alpha/tru64/tru64.hh
index 19343ba23..f0711b995 100644
--- a/src/arch/alpha/tru64/tru64.hh
+++ b/src/arch/alpha/tru64/tru64.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ALPHA_ALPHA_TRU64_HH
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index d4cb482d8..5859052e9 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
  */
 
 #ifndef __ARCH_ALPHA_TYPES_HH__
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 6cc916307..ec136091c 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
  */
 
 #ifndef __ARCH_ALPHA_UTILITY_HH__
@@ -106,10 +109,10 @@ namespace AlphaISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
 
 #if FULL_SYSTEM
     // Alpha IPR register accessors
@@ -140,15 +143,15 @@ namespace AlphaISA
     RoundPage(Addr addr)
     { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
-    void initCPU(ExecContext *xc, int cpuId);
-    void initIPRs(ExecContext *xc, int cpuId);
+    void initCPU(ThreadContext *tc, int cpuId);
+    void initIPRs(ThreadContext *tc, int cpuId);
 
     /**
      * Function to check for and process any interrupts.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void processInterrupts(XC *xc);
+    template <class TC>
+    void processInterrupts(TC *tc);
 #endif
 
 } // namespace AlphaISA
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index 41e9b80a3..f7fd92c15 100644
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -24,6 +24,10 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Ali Saidi
  */
 
 #include <string>
@@ -32,7 +36,7 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/vport.hh"
 
 using namespace std;
@@ -81,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr)
 }
 
 Addr
-AlphaISA::vtophys(ExecContext *xc, Addr addr)
+AlphaISA::vtophys(ThreadContext *tc, Addr addr)
 {
     AlphaISA::VAddr vaddr = addr;
-    Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
+    Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
     Addr paddr = 0;
     //@todo Andrew couldn't remember why he commented some of this code
     //so I put it back in. Perhaps something to do with gdb debugging?
@@ -97,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr)
             paddr = vaddr;
         } else {
             AlphaISA::PageTableEntry pte =
-                kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
+                kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
             if (pte.valid())
                 paddr = pte.paddr() | vaddr.offset();
         }
@@ -111,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr)
 
 
 void
-AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
+AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
 {
     uint8_t *dst = (uint8_t *)dest;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     vp->readBlob(src, dst, cplen);
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 
 }
 
 void
-AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
+AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
 {
     uint8_t *src = (uint8_t *)source;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     vp->writeBlob(dest, src, cplen);
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 }
 
 void
-AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
+AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
 {
     int len = 0;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     do {
         vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
         len++;
     } while (len < maxlen && dst[len] != 0 );
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
     dst[len] = 0;
 }
 
 void
-AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
+AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
 {
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
     for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
             gen.next())
     {
         vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
         src += gen.size();
     }
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 }
diff --git a/src/arch/alpha/vtophys.hh b/src/arch/alpha/vtophys.hh
index 7ab14bc5b..472c694ff 100644
--- a/src/arch/alpha/vtophys.hh
+++ b/src/arch/alpha/vtophys.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
  */
 
 #ifndef __ARCH_ALPHA_VTOPHYS_H__
@@ -31,7 +34,7 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-class ExecContext;
+class ThreadContext;
 class FunctionalPort;
 
 namespace AlphaISA {
@@ -40,12 +43,12 @@ PageTableEntry
 kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
 
 Addr vtophys(Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ExecContext *xc, char *src, Addr vaddr);
+void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
 
 };
 #endif // __ARCH_ALPHA_VTOPHYS_H__
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index c0758da50..4d522e18a 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -23,6 +23,9 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Korey Sewell
 
 import os
 import sys
@@ -1179,6 +1182,11 @@ class IntRegOperand(Operand):
         if (self.size == self.dflt_size):
             return '%s = xc->readIntReg(this, %d);\n' % \
                    (self.base_name, self.src_reg_idx)
+        elif (self.size > self.dflt_size):
+            int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+            if (self.is_signed):
+                int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
+            return '%s = %s;\n' % (self.base_name, int_reg_val)
         else:
             return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
                    (self.base_name, self.src_reg_idx, self.size-1)
diff --git a/src/arch/isa_specific.hh b/src/arch/isa_specific.hh
index 91c9ffb68..181e81302 100644
--- a/src/arch/isa_specific.hh
+++ b/src/arch/isa_specific.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
  */
 
 #ifndef __ARCH_ISA_SPECIFIC_HH__
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index ef1ef25d6..8353bcde7 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -25,6 +25,10 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+#          Steve Reinhardt
+#          Korey Sewell
 
 import os
 import sys
@@ -43,16 +47,12 @@ Import('env')
 base_sources = Split('''
 	faults.cc
 	isa_traits.cc
+        utility.cc
 	''')
 
 # Full-system sources
 full_system_sources = Split('''
-	memory.cc
-	arguments.cc
-	mips34k.cc
-	osfpal.cc
-	stacktrace.cc
-	vtophys.cc
+	#Insert Full-System Files Here
 	''')
 
 # Syscall emulation (non-full-system) sources
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 1b31dfa69..cfeb045eb 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -24,12 +24,18 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #include "arch/mips/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
+#if !FULL_SYSTEM
+#include "sim/process.hh"
+#include "mem/page_table.hh"
+#endif
 
 namespace MipsISA
 {
@@ -50,6 +56,12 @@ FaultName ArithmeticFault::_name = "arith";
 FaultVect ArithmeticFault::_vect = 0x0501;
 FaultStat ArithmeticFault::_count;
 
+#if !FULL_SYSTEM
+FaultName PageTableFault::_name = "page_table_fault";
+FaultVect PageTableFault::_vect = 0x0000;
+FaultStat PageTableFault::_count;
+#endif
+
 FaultName InterruptFault::_name = "interrupt";
 FaultVect InterruptFault::_vect = 0x0101;
 FaultStat InterruptFault::_count;
@@ -100,32 +112,53 @@ FaultStat IntegerOverflowFault::_count;
 
 #if FULL_SYSTEM
 
-void MipsFault::invoke(ExecContext * xc)
+void MipsFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     countStat()++;
 
     // exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
+    if (setRestartAddress() || !tc->inPalMode())
+        tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
+                   tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
     }
 
-    xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
-    xc->setNextPC(xc->readPC() + sizeof(MachInst));
+    tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
+    tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
-#endif
+#else //!FULL_SYSTEM
 
+void PageTableFault::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+
+    // address is higher than the stack region or in the current stack region
+    if (vaddr > p->stack_base || vaddr > p->stack_min)
+        FaultBase::invoke(tc);
+
+    // We've accessed the next page
+    if (vaddr > p->stack_min - PageBytes) {
+        p->stack_min -= PageBytes;
+        if (p->stack_base - p->stack_min > 8*1024*1024)
+            fatal("Over max stack size for one thread\n");
+        p->pTable->allocate(p->stack_min, PageBytes);
+        warn("Increasing stack size by one page.");
+    } else {
+        FaultBase::invoke(tc);
+    }
+}
+
+#endif
 } // namespace MipsISA
 
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 0bdabe29e..95c61cfbc 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __MIPS_FAULTS_HH__
@@ -45,7 +47,7 @@ class MipsFault : public FaultBase
     virtual bool setRestartAddress() {return true;}
   public:
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -77,6 +79,30 @@ class AlignmentFault : public MipsFault
     bool isAlignmentFault() {return true;}
 };
 
+#if !FULL_SYSTEM
+class PageTableFault : public MipsFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    PageTableFault(Addr va)
+        : vaddr(va) {}
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+static inline Fault genPageTableFault(Addr va)
+{
+    return new PageTableFault(va);
+}
+#endif
+
+
 static inline Fault genMachineCheckFault()
 {
     return new MachineCheckFault;
@@ -112,7 +138,7 @@ class ArithmeticFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index b2a31c018..f07b06e03 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Base class for MIPS instructions, and some support functions
@@ -10,7 +38,6 @@ output header {{
 
     using namespace MipsISA;
 
-
     /**
      * Base class for all MIPS static instructions.
      */
@@ -18,16 +45,6 @@ output header {{
     {
       protected:
 
-        /// Make MipsISA register dependence tags directly visible in
-        /// this class and derived classes.  Maybe these should really
-        /// live here and not in the MipsISA namespace.
-        /*enum DependenceTags {
-            FP_Base_DepTag = MipsISA::FP_Base_DepTag,
-            Fpcr_DepTag = MipsISA::Fpcr_DepTag,
-            Uniq_DepTag = MipsISA::Uniq_DepTag,
-            IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
-            };*/
-
         // Constructor
         MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
             : StaticInst(mnem, _machInst, __opClass)
@@ -67,12 +84,12 @@ output decoder {{
         }
 
         if(_numSrcRegs > 0) {
-            ss << ",";
+            ss << ", ";
             printReg(ss, _srcRegIdx[0]);
         }
 
         if(_numSrcRegs > 1) {
-            ss << ",";
+            ss << ", ";
             printReg(ss, _srcRegIdx[1]);
         }
 
diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa
index e1124a591..35815bf1f 100644
--- a/src/arch/mips/isa/bitfields.isa
+++ b/src/arch/mips/isa/bitfields.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Bitfield definitions.
@@ -17,20 +45,19 @@ def bitfield FUNCTION      < 5: 0>;
 def bitfield FUNCTION_HI   < 5: 3>;
 def bitfield FUNCTION_LO   < 2: 0>;
 
-// Integer operate format
-def bitfield RT	      <20:16>;
-def bitfield RT_HI    <20:19>;
-def bitfield RT_LO    <18:16>;
-
 def bitfield RS	      <25:21>;
 def bitfield RS_MSB   <25:25>;
 def bitfield RS_HI    <25:24>;
 def bitfield RS_LO    <23:21>;
-def bitfield RS_SRL    <25:22>;
-
+def bitfield RS_SRL   <25:22>;
+def bitfield RS_RT    <25:16>;
+def bitfield RT	      <20:16>;
+def bitfield RT_HI    <20:19>;
+def bitfield RT_LO    <18:16>;
+def bitfield RT_RD    <20:11>;
 def bitfield RD	      <15:11>;
 
-def bitfield INTIMM	<15: 0>; // integer immediate (literal)
+def bitfield INTIMM	  <15: 0>;
 
 // Floating-point operate format
 def bitfield FMT      <25:21>;
@@ -67,5 +94,9 @@ def bitfield HINT	<10: 6>;
 def bitfield SYSCALLCODE <25: 6>;
 def bitfield TRAPCODE    <15:13>;
 
+// EXT/INS instructions
+def bitfield MSB	<15:11>;
+def bitfield LSB	<10: 6>;
+
 // M5 instructions
 def bitfield M5FUNC <7:0>;
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 1454aba39..9ac982e34 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1,4 +1,32 @@
- // -*- mode:c++ -*-
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -6,41 +34,33 @@
 // -----------------------------
 // The following instructions are specified in the MIPS32 ISA
 // Specification. Decoding closely follows the style specified
-// in the MIPS32 ISAthe specification document starting with Table
+// in the MIPS32 ISA specification document starting with Table
 // A-2 (document available @ www.mips.com)
 //
-//@todo: Distinguish "unknown/future" use insts from "reserved"
-// ones
 decode OPCODE_HI default Unknown::unknown() {
-
-    // Derived From ... Table A-2 MIPS32 ISA Manual
+    //Table A-2
     0x0: decode OPCODE_LO {
-
         0x0: decode FUNCTION_HI {
             0x0: decode FUNCTION_LO {
                 0x1: decode MOVCI {
                     format BasicOp {
-                        0: movf({{ if (getFPConditionCode(FCSR, CC) == 0) Rd = Rs}});
-                        1: movt({{ if (getFPConditionCode(FCSR, CC) == 1) Rd = Rs}});
+                        0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
+                        1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
                     }
                 }
 
                 format BasicOp {
-
-                    //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
-                    //are used to distinguish among the SLL, NOP, SSNOP and EHB functions.
+                    //Table A-3 Note: "Specific encodings of the rd, rs, and
+                    //rt fields are used to distinguish SLL, SSNOP, and EHB
+                    //functions
                     0x0: decode RS  {
-                        0x0: decode RT {     //fix Nop traditional vs. Nop converted disassembly later
-                             0x0: decode RD  default Nop::nop(){
-                                  0x0: decode SA {
-                                      0x1: ssnop({{ ; }}); //really sll r0,r0,1
-                                      0x3: ehb({{ ; }});   //really sll r0,r0,3
-                                  }
-                             }
-
-                             default: sll({{ Rd = Rt.uw << SA; }});
+                        0x0: decode RT_RD {
+                            0x0: decode SA default Nop::nop(){
+                                0x1: WarnUnimpl::ssnop();
+                                0x3: WarnUnimpl::ehb();
+                            }
+                            default: sll({{ Rd = Rt.uw << SA; }});
                         }
-
                     }
 
                     0x2: decode RS_SRL {
@@ -55,7 +75,6 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x3: decode RS {
                         0x0: sra({{
                             uint32_t temp = Rt >> SA;
-
                             if ( (Rt & 0x80000000) > 0 ) {
                                 uint32_t mask = 0x80000000;
                                 for(int i=0; i < SA; i++) {
@@ -63,7 +82,6 @@ decode OPCODE_HI default Unknown::unknown() {
                                     mask = mask >> 1;
                                 }
                             }
-
                             Rd = temp;
                         }});
                     }
@@ -96,37 +114,36 @@ decode OPCODE_HI default Unknown::unknown() {
             }
 
             0x1: decode FUNCTION_LO {
-
-                //Table A-3 Note: "Specific encodings of the hint field are used
-                //to distinguish JR from JR.HB and JALR from JALR.HB"
+                //Table A-3 Note: "Specific encodings of the hint field are
+                //used to distinguish JR from JR.HB and JALR from JALR.HB"
                 format Jump {
                     0x0: decode HINT {
-                        0:jr({{ NNPC = Rs & ~1; }},IsReturn);
-
-                        1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
+                        0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
+                        default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
                     }
 
                     0x1: decode HINT {
-                        0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn);
-
-                        1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
+                        0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link
+                                     , ClearHazards);
+                        default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall,
+                                      Link);
                     }
                 }
 
                 format BasicOp {
-                    0x2: movz({{ if (Rt == 0) Rd = Rs; }});
-                    0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+                    0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
+                    0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
+                    0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative);
+                    0x7: sync({{ ; }}, IsMemBarrier);
                 }
 
-                format BasicOp {
-                    0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
-                    0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
-                    0x7: sync({{  panic("Not implemented sync yet"); }},IsNonSpeculative);
+                format FailUnimpl {
+                    0x5: break();
                 }
             }
 
             0x2: decode FUNCTION_LO {
-                format BasicOp {
+                format HiLoMiscOp {
                     0x0: mfhi({{ Rd = HI; }});
                     0x1: mthi({{ HI = Rs; }});
                     0x2: mflo({{ Rd = LO; }});
@@ -135,28 +152,22 @@ decode OPCODE_HI default Unknown::unknown() {
             }
 
             0x3: decode FUNCTION_LO {
-                format IntOp {
-                    0x0: mult({{
-                        int64_t temp1 = Rs.sd * Rt.sd;
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
-
-                    0x1: multu({{
-                        uint64_t temp1 = Rs.ud * Rt.ud;
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
-
-                    0x2: div({{
-                        HI = Rs.sd % Rt.sd;
-                        LO = Rs.sd / Rt.sd;
-                    }});
+                format HiLoOp {
+                    0x0: mult({{ val = Rs.sd * Rt.sd; }});
+                    0x1: multu({{ val = Rs.ud * Rt.ud; }});
+                }
 
-                    0x3: divu({{
-                        HI = Rs.ud % Rt.ud;
-                        LO = Rs.ud / Rt.ud;
-                    }});
+                format HiLoMiscOp {
+                    0x2: div({{ if (Rt.sd != 0) {
+                                    HI = Rs.sd % Rt.sd;
+                                    LO = Rs.sd / Rt.sd;
+                                }
+                             }});
+                    0x3: divu({{ if (Rt.ud != 0) {
+                                     HI = Rs.ud % Rt.ud;
+                                     LO = Rs.ud / Rt.ud;
+                                 }
+                              }});
                 }
             }
 
@@ -201,11 +212,8 @@ decode OPCODE_HI default Unknown::unknown() {
                 format Branch {
                     0x0: bltz({{ cond = (Rs.sw < 0); }});
                     0x1: bgez({{ cond = (Rs.sw >= 0); }});
-                }
-
-                format BranchLikely {
-                    0x2: bltzl({{ cond = (Rs.sw < 0); }});
-                    0x3: bgezl({{ cond = (Rs.sw >= 0); }});
+                    0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
+                    0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
                 }
             }
 
@@ -222,13 +230,13 @@ decode OPCODE_HI default Unknown::unknown() {
 
             0x2: decode REGIMM_LO {
                 format Branch {
-                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
-                    0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
-                }
-
-                format BranchLikely {
-                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
-                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
+                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
+                    0x1: decode RS {
+                        0x0: bal ({{ cond = 1; }}, IsCall, Link);
+                        default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
+                    }
+                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
+                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
                 }
             }
 
@@ -241,25 +249,23 @@ decode OPCODE_HI default Unknown::unknown() {
 
         format Jump {
             0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
-
-            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
+            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
+                     Link);
         }
 
         format Branch {
-            0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
-            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
-            0x6: decode RT {
-                0x0: blez({{ cond = (Rs.sw <= 0); }});
-            }
-
-            0x7: decode RT {
-                0x0: bgtz({{ cond = (Rs.sw > 0); }});
+            0x4: decode RS_RT  {
+                0x0: b({{ cond = 1; }});
+                default: beq({{ cond = (Rs.sw == Rt.sw); }});
             }
+            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
+            0x6: blez({{ cond = (Rs.sw <= 0); }});
+            0x7: bgtz({{ cond = (Rs.sw > 0); }});
         }
     }
 
     0x1: decode OPCODE_LO {
-        format IntOp {
+        format IntImmOp {
             0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
             0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
             0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
@@ -275,112 +281,47 @@ decode OPCODE_HI default Unknown::unknown() {
     }
 
     0x2: decode OPCODE_LO {
-
         //Table A-11 MIPS32 COP0 Encoding of rs Field
         0x0: decode RS_MSB {
             0x0: decode RS {
-                format System {
-                    0x0: mfc0({{
-                        //uint64_t reg_num = Rd.uw;
-
-                        Rt = xc->readMiscReg(RD << 5 | SEL);
-                    }});
-
-                    0x4: mtc0({{
-                        //uint64_t reg_num = Rd.uw;
-
-                        xc->setMiscReg(RD << 5 | SEL,Rt);
-                    }});
-
-                    0x8: mftr({{
-                        //The contents of the coprocessor 0 register specified by the
-                        //combination of rd and sel are loaded into general register
-                        //rt. Note that not all coprocessor 0 registers support the
-                        //sel field. In those instances, the sel field must be zero.
-
-                        //MT Code Needed Here
-
-                    }});
-
-                    0xC: mttr({{
-                        //The contents of the coprocessor 0 register specified by the
-                        //combination of rd and sel are loaded into general register
-                        //rt. Note that not all coprocessor 0 registers support the
-                        //sel field. In those instances, the sel field must be zero.
-
-                        //MT Code Needed Here
-                    }});
-
-
-                    0xA: rdpgpr({{
-                        //Accessing Previous Shadow Set Register Number
-                        //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
-                        //uint64_t reg_num = Rt.uw;
-
-                        //Rd = xc->regs.IntRegFile[prev];
-                       //Rd = xc->shadowIntRegFile[prev][reg_num];
-                    }});
+                format CP0Control {
+                    0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
+                    0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
+                }
 
+                format MipsMT {
+                    0x8: mftr();
+                    0xC: mttr();
                     0xB: decode RD {
-
                         0x0: decode SC {
-                            0x0: dvpe({{
-                                Rt.sw = xc->readMiscReg(MVPControl);
-                                xc->setMiscReg(MVPControl,0);
-                            }});
-
-                            0x1: evpe({{
-                                Rt.sw = xc->readMiscReg(MVPControl);
-                                xc->setMiscReg(MVPControl,1);
-                            }});
+                            0x0: dvpe();
+                            0x1: evpe();
                         }
-
                         0x1: decode SC {
-                            0x0: dmt({{
-                                Rt.sw = xc->readMiscReg(VPEControl);
-                                xc->setMiscReg(VPEControl,0);
-                            }});
-
-                            0x1: emt({{
-                                Rt.sw = xc->readMiscReg(VPEControl);
-                                xc->setMiscReg(VPEControl,1);
-                            }});
-                        }
-
-                        0xC: decode SC {
-                            0x0: di({{
-                                Rt.sw = xc->readMiscReg(Status);
-                                xc->setMiscReg(Status,0);
-                            }});
-
-                            0x1: ei({{
-                                Rt.sw = xc->readMiscReg(Status);
-                                xc->setMiscReg(Status,1);
-                            }});
+                            0x0: dmt();
+                            0x1: emt();
+                            0xC: decode SC {
+                                0x0: di();
+                                0x1: ei();
+                            }
                         }
                     }
+                }
 
-                    0xE: wrpgpr({{
-                        //Accessing Previous Shadow Set Register Number
-                        //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
-                        //uint64_t reg_num = Rd.uw;
-
-                        //xc->regs.IntRegFile[prev];
-                        //xc->shadowIntRegFile[prev][reg_num] = Rt;
-                    }});
+                format FailUnimpl {
+                    0xA: rdpgpr();
+                    0xE: wrpgpr();
                 }
             }
 
             //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
             0x1: decode FUNCTION {
-                format System {
-                    0x01: tlbr({{ }});
-                    0x02: tlbwi({{ }});
-                    0x06: tlbwr({{ }});
-                    0x08: tlbp({{ }});
-                }
+                format FailUnimpl {
+                    0x01: tlbr();
+                    0x02: tlbwi();
+                    0x06: tlbwr();
+                    0x08: tlbp();
 
-                format WarnUnimpl {
                     0x18: eret();
                     0x1F: deret();
                     0x20: wait();
@@ -393,18 +334,9 @@ decode OPCODE_HI default Unknown::unknown() {
 
             0x0: decode RS_HI {
                 0x0: decode RS_LO {
-                    format FloatOp {
-                        0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
-                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
-                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
-                        0x7: mthc1({{
-                             uint64_t fs_hi = Rt.uw;
-                             uint64_t fs_lo = Fs.ud & 0x0000FFFF;
-                             Fs.ud = fs_hi << 32 | fs_lo;
-                        }});
-                    }
+                    format CP1Control {
+                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
 
-                    format System {
                         0x2: cfc1({{
                             switch (FS)
                             {
@@ -424,11 +356,14 @@ decode OPCODE_HI default Unknown::unknown() {
                                 Rt = FCSR;
                                 break;
                               default:
-                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
-                                      "Floating Control Status Register",FS);
+                                panic("FP Control Value (%d) Not Valid");
                             }
                         }});
 
+                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
+
+                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
+
                         0x6: ctc1({{
                             switch (FS)
                             {
@@ -464,21 +399,29 @@ decode OPCODE_HI default Unknown::unknown() {
                                       "Floating Control Status Register", FS);
                             }
                         }});
+
+                        0x7: mthc1({{
+                             uint64_t fs_hi = Rt.uw;
+                             uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
+                             Fs.ud = (fs_hi << 32) | fs_lo;
+                        }});
+
                     }
                 }
 
                 0x1: decode ND {
-                    0x0: decode TF {
-                        format Branch {
-                            0x0: bc1f({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
-                            0x1: bc1t({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
+                    format Branch {
+                        0x0: decode TF {
+                            0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
+                                      }});
+                            0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
+                                      }});
                         }
-                    }
-
-                    0x1: decode TF {
-                        format BranchLikely {
-                            0x0: bc1fl({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
-                            0x1: bc1tl({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
+                        0x1: decode TF {
+                            0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
+                                       }}, Likely);
+                            0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
+                                       }}, Likely);
                         }
                     }
                 }
@@ -486,9 +429,8 @@ decode OPCODE_HI default Unknown::unknown() {
 
             0x1: decode RS_HI {
                 0x2: decode RS_LO {
-
                     //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
-                    //(( single-word ))
+                    //(( single-precision floating point))
                     0x0: decode FUNCTION_HI {
                         0x0: decode FUNCTION_LO {
                             format FloatOp {
@@ -498,195 +440,104 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
                                 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
                                 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
-                                0x6: mov_s({{ Fd.sf = Fs.sf;}});
-                                0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}});
+                                0x7: neg_s({{ Fd.sf = -Fs.sf;}});
                             }
+
+                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
                         }
 
                         0x1: decode FUNCTION_LO {
-                            format Float64Op {
-                                0x0: round_l_s({{
-                                    Fd.ud = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_LONG);
-                                }});
-
-                                0x1: trunc_l_s({{
-                                    Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG);
-                                }});
-
-                                0x2: ceil_l_s({{
-                                    Fd.ud = fpConvert(ceil(Fs.sf),  SINGLE_TO_LONG);
-                                }});
-
-                                0x3: floor_l_s({{
-                                    Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG);
-                                }});
-                            }
-
-                            format FloatOp {
-                                0x4: round_w_s({{
-                                    Fd.uw = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_WORD);
-                                }});
-
-                                0x5: trunc_w_s({{
-                                    Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD);
-                                }});
-
-                                0x6: ceil_w_s({{
-                                    Fd.uw = fpConvert(ceil(Fs.sf),  SINGLE_TO_WORD);
-                                }});
-
-                                0x7: floor_w_s({{
-                                    Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD);
-                                }});
+                            format FloatConvertOp {
+                                0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
+                                               Round);
+                                0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
+                                               Trunc);
+                                0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
+                                               Ceil);
+                                0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
+                                               Floor);
+                                0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
+                                               Round);
+                                0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
+                                               Trunc);
+                                0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
+                                               Ceil);
+                                0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
+                                               Floor);
                             }
                         }
 
                         0x2: decode FUNCTION_LO {
                             0x1: decode MOVCF {
-                                format FloatOp {
-                                    0x0: movf_s({{if (getFPConditionCode(FCSR,CC) == 0) Fd = Fs;}});
-                                    0x1: movt_s({{if (getFPConditionCode(FCSR,CC) == 1) Fd = Fs;}});
+                                format BasicOp {
+                                    0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
+                                    0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
                                 }
                             }
 
+                            format BasicOp {
+                                0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
+                                0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
+                            }
+
                             format FloatOp {
-                                0x2: movz_s({{ if (Rt == 0) Fd = Fs; }});
-                                0x3: movn_s({{ if (Rt != 0) Fd = Fs; }});
                                 0x5: recip_s({{ Fd = 1 / Fs; }});
                                 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
                             }
                         }
 
                         0x4: decode FUNCTION_LO {
-
                             format FloatConvertOp {
-                                0x1: cvt_d_s({{
-                                    Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE);
-                                }});
-
-                                0x4: cvt_w_s({{
-                                    Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD);
-                                }});
+                                0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
+                                0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
+                                0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
                             }
 
-                            format FloatConvertOp {
-                                0x5: cvt_l_s({{
-                                    Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG);
-                                }});
-
-                                0x6: cvt_ps_st({{
-                                    Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw;
+                            0x6: FloatOp::cvt_ps_s({{
+                                    Fd.ud = (uint64_t) Fs.uw << 32 |
+                                            (uint64_t) Ft.uw;
                                 }});
-                            }
                         }
 
                         0x6: decode FUNCTION_LO {
                             format FloatCompareOp {
-                                0x0: c_f_s({{ cond = 0; }});
-
-                                0x1: c_un_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = 0;
-                                }});
-
-                                0x2: c_eq_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf == Ft.sf);
-                                }});
-
-                                0x3: c_ueq_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf == Ft.sf);
-                                }});
-
-                                0x4: c_olt_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf < Ft.sf);
-                                }});
-
-                                0x5: c_ult_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf < Ft.sf);
-                                }});
-
-                                0x6: c_ole_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf <= Ft.sf);
-                                }});
-
-                                0x7: c_ule_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf <= Ft.sf);
-                                }});
+                                0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
+                                           UnorderedFalse);
+                                0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
+                                            UnorderedTrue);
+                                0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
+                                            UnorderedFalse);
+                                0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
+                                             UnorderedTrue);
+                                0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf);	}},
+                                             UnorderedFalse);
+                                0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
+                                             UnorderedTrue);
+                                0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
+                                             UnorderedFalse);
+                                0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
+                                             UnorderedTrue);
                             }
                         }
 
                         0x7: decode FUNCTION_LO {
-                            format FloatCompareWithXcptOp {
-                                0x0: c_sf_s({{ cond = 0; }});
-
-                                0x1: c_ngle_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = 0;
-                                  }});
-
-                                0x2: c_seq_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf == Ft.sf);
-                                  }});
-
-                                0x3: c_ngl_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf == Ft.sf);
-                                  }});
-
-                                0x4: c_lt_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf < Ft.sf);
-                                  }});
-
-                                0x5: c_nge_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf < Ft.sf);
-                                  }});
-
-                                0x6: c_le_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.sf <= Ft.sf);
-                                  }});
-
-                                0x7: c_ngt_s({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.sf <= Ft.sf);
-                                  }});
+                            format FloatCompareOp {
+                                0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
+                                            UnorderedFalse, QnanException);
+                                0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
+                                              UnorderedTrue, QnanException);
+                                0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
+                                             UnorderedFalse, QnanException);
+                                0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
+                                             UnorderedTrue, QnanException);
+                                0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
+                                            UnorderedFalse, QnanException);
+                                0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
+                                             UnorderedTrue, QnanException);
+                                0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
+                                            UnorderedFalse, QnanException);
+                                0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
+                                             UnorderedTrue, QnanException);
                             }
                         }
                     }
@@ -695,197 +546,109 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x1: decode FUNCTION_HI {
                         0x0: decode FUNCTION_LO {
                             format FloatOp {
-                                0x0: add_d({{ Fd.df = Fs.df + Ft.df;}});
-                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df;}});
-                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df;}});
-                                0x3: div_d({{ Fd.df = Fs.df / Ft.df;}});
-                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);}});
-                                0x5: abs_d({{ Fd.df = fabs(Fs.df);}});
-                                0x6: mov_d({{ Fd.ud = Fs.ud;}});
-                                0x7: neg_d({{ Fd.df = -1 * Fs.df;}});
+                                0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
+                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
+                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
+                                0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
+                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);  }});
+                                0x5: abs_d({{ Fd.df = fabs(Fs.df);   }});
+                                0x7: neg_d({{ Fd.df = -1 * Fs.df;    }});
                             }
+
+                            0x6: BasicOp::mov_d({{ Fd.df = Fs.df;    }});
                         }
 
                         0x1: decode FUNCTION_LO {
-                            format FloatOp {
-                                0x0: round_l_d({{
-                                    Fd.ud = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_LONG);
-                                }});
-
-                                0x1: trunc_l_d({{
-                                    Fd.ud = fpConvert(truncFP(Fs.df), DOUBLE_TO_LONG);
-                                }});
-
-                                0x2: ceil_l_d({{
-                                    Fd.ud = fpConvert(ceil(Fs.df), DOUBLE_TO_LONG);
-                                }});
-
-                                0x3: floor_l_d({{
-                                    Fd.ud = fpConvert(floor(Fs.df), DOUBLE_TO_LONG);
-                                }});
-                            }
-
-                            format FloatOp {
-                                0x4: round_w_d({{
-                                    Fd.uw = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_WORD);
-                                }});
-
-                                0x5: trunc_w_d({{
-                                    Fd.uw = fpConvert(truncFP(Fs.df), DOUBLE_TO_WORD);
-                                }});
-
-                                0x6: ceil_w_d({{
-                                    Fd.uw = fpConvert(ceil(Fs.df), DOUBLE_TO_WORD);
-                                }});
-
-                                0x7: floor_w_d({{
-                                    Fd.uw = fpConvert(floor(Fs.df), DOUBLE_TO_WORD);
-                                }});
+                            format FloatConvertOp {
+                                0x0: round_l_d({{ val = Fs.df; }}, ToLong,
+                                               Round);
+                                0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
+                                               Trunc);
+                                0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
+                                               Ceil);
+                                0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
+                                               Floor);
+                                0x4: round_w_d({{ val = Fs.df; }}, ToWord,
+                                               Round);
+                                0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
+                                               Trunc);
+                                0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
+                                               Ceil);
+                                0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
+                                               Floor);
                             }
                         }
 
                         0x2: decode FUNCTION_LO {
                             0x1: decode MOVCF {
-                                format FloatOp {
-                                    0x0: movf_d({{if (getFPConditionCode(FCSR,CC) == 0) Fd.df = Fs.df; }});
-                                    0x1: movt_d({{if (getFPConditionCode(FCSR,CC) == 1) Fd.df = Fs.df; }});
+                                format BasicOp {
+                                    0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
+                                                       Fs.df : Fd.df;
+                                                }});
+                                    0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
+                                                       Fs.df : Fd.df;
+                                                }});
                                 }
                             }
 
                             format BasicOp {
-                                0x2: movz_d({{ if (Rt == 0) Fd.df = Fs.df; }});
-                                0x3: movn_d({{ if (Rt != 0) Fd.df = Fs.df; }});
+                                0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
+                                0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
                             }
 
                             format FloatOp {
-                                0x5: recip_d({{ Fd.df = 1 / Fs.df}});
+                                0x5: recip_d({{ Fd.df = 1 / Fs.df }});
                                 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
                             }
                         }
 
                         0x4: decode FUNCTION_LO {
-                            format FloatOp {
-                                0x0: cvt_s_d({{
-                                    Fd.uw = fpConvert(Fs.df, DOUBLE_TO_SINGLE);
-                                }});
-
-                                0x4: cvt_w_d({{
-                                    Fd.uw = fpConvert(Fs.df, DOUBLE_TO_WORD);
-                                }});
-
-                                0x5: cvt_l_d({{
-                                    Fd.ud = fpConvert(Fs.df, DOUBLE_TO_LONG);
-                                }});
+                            format FloatConvertOp {
+                                0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
+                                0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
+                                0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
                             }
                         }
 
                         0x6: decode FUNCTION_LO {
                             format FloatCompareOp {
-                                0x0: c_f_d({{ cond = 0; }});
-
-                                0x1: c_un_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = 0;
-                                }});
-
-                                0x2: c_eq_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df == Ft.df);
-                                }});
-
-                                0x3: c_ueq_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df == Ft.df);
-                                }});
-
-                                0x4: c_olt_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df < Ft.df);
-                                }});
-
-                                0x5: c_ult_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df < Ft.df);
-                                }});
-
-                                0x6: c_ole_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df <= Ft.df);
-                                }});
-
-                                0x7: c_ule_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df <= Ft.df);
-                                }});
+                                0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
+                                           UnorderedFalse);
+                                0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
+                                            UnorderedTrue);
+                                0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
+                                            UnorderedFalse);
+                                0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
+                                             UnorderedTrue);
+                                0x4: c_olt_d({{ cond = (Fs.df < Ft.df);	}},
+                                             UnorderedFalse);
+                                0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
+                                             UnorderedTrue);
+                                0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
+                                             UnorderedFalse);
+                                0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
+                                             UnorderedTrue);
                             }
                         }
 
                         0x7: decode FUNCTION_LO {
-                            format FloatCompareWithXcptOp {
-                                0x0: c_sf_d({{ cond = 0; }});
-
-                                0x1: c_ngle_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = 0;
-                                  }});
-
-                                0x2: c_seq_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df == Ft.df);
-                                  }});
-
-                                0x3: c_ngl_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df == Ft.df);
-                                  }});
-
-                                0x4: c_lt_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df < Ft.df);
-                                  }});
-
-                                0x5: c_nge_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df < Ft.df);
-                                  }});
-
-                                0x6: c_le_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 0;
-                                    else
-                                        cond = (Fs.df <= Ft.df);
-                                  }});
-
-                                0x7: c_ngt_d({{
-                                    if (isnan(Fs.df) || isnan(Ft.df))
-                                        cond = 1;
-                                    else
-                                        cond = (Fs.df <= Ft.df);
-                                  }});
+                            format FloatCompareOp {
+                                0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
+                                            UnorderedFalse, QnanException);
+                                0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
+                                              UnorderedTrue, QnanException);
+                                0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
+                                             UnorderedFalse, QnanException);
+                                0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
+                                             UnorderedTrue, QnanException);
+                                0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
+                                            UnorderedFalse, QnanException);
+                                0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
+                                             UnorderedTrue, QnanException);
+                                0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
+                                            UnorderedFalse, QnanException);
+                                0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
+                                             UnorderedTrue, QnanException);
                             }
                         }
                     }
@@ -893,19 +656,9 @@ decode OPCODE_HI default Unknown::unknown() {
                     //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
                     0x4: decode FUNCTION {
                         format FloatConvertOp {
-                            0x20: cvt_s_w({{
-                                Fd.uw = fpConvert(Fs.sf, WORD_TO_SINGLE);
-                            }});
-
-                            0x21: cvt_d_w({{
-                                Fd.ud = fpConvert(Fs.sf, WORD_TO_DOUBLE);
-                            }});
-                        }
-
-                        format Float64ConvertOp {
-                            0x26: cvt_ps_pw({{
-                                Fd.ud = fpConvert(Fs.ud, WORD_TO_PS);
-                            }});
+                            0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
+                            0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
+                            0x26: FailUnimpl::cvt_ps_w();
                         }
                     }
 
@@ -913,18 +666,10 @@ decode OPCODE_HI default Unknown::unknown() {
                     //Note: "1. Format type L is legal only if 64-bit floating point operations
                     //are enabled."
                     0x5: decode FUNCTION_HI {
-                        format Float64ConvertOp {
-                            0x20: cvt_s_l({{
-                                Fd.uw = fpConvert(Fs.ud, LONG_TO_SINGLE);
-                            }});
-
-                            0x21: cvt_d_l({{
-                                Fd.ud = fpConvert(Fs.ud, LONG_TO_DOUBLE);
-                            }});
-
-                            0x26: cvt_ps_l({{
-                                Fd.ud = fpConvert(Fs.ud, LONG_TO_PS);
-                            }});
+                        format FloatConvertOp {
+                            0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
+                            0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
+                            0x26: FailUnimpl::cvt_ps_l();
                         }
                     }
 
@@ -938,30 +683,25 @@ decode OPCODE_HI default Unknown::unknown() {
                                     Fd1.sf = Fs1.sf + Ft2.sf;
                                     Fd2.sf = Fs2.sf + Ft2.sf;
                                 }});
-
                                 0x1: sub_ps({{
                                     Fd1.sf = Fs1.sf - Ft2.sf;
                                     Fd2.sf = Fs2.sf - Ft2.sf;
                                 }});
-
                                 0x2: mul_ps({{
                                     Fd1.sf = Fs1.sf * Ft2.sf;
                                     Fd2.sf = Fs2.sf * Ft2.sf;
                                 }});
-
                                 0x5: abs_ps({{
                                     Fd1.sf = fabs(Fs1.sf);
                                     Fd2.sf = fabs(Fs2.sf);
                                 }});
-
                                 0x6: mov_ps({{
                                     Fd1.sf = Fs1.sf;
                                     Fd2.sf = Fs2.sf;
                                 }});
-
                                 0x7: neg_ps({{
-                                    Fd1.sf = -1 * Fs1.sf;
-                                    Fd2.sf = -1 * Fs2.sf;
+                                    Fd1.sf = -(Fs1.sf);
+                                    Fd2.sf = -(Fs2.sf);
                                 }});
                             }
                         }
@@ -970,236 +710,112 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x1: decode MOVCF {
                                 format Float64Op {
                                     0x0: movf_ps({{
-                                        if (getFPConditionCode(FCSR, CC) == 0)
-                                            Fd1 = Fs1;
-                                        if (getFPConditionCode(FCSR, CC+1) == 0)
-                                            Fd2 = Fs2;
+                                        Fd1 = (getCondCode(FCSR, CC) == 0) ?
+                                            Fs1 : Fd1;
+                                        Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
+                                            Fs2 : Fd2;
                                     }});
-
                                     0x1: movt_ps({{
-                                        if (getFPConditionCode(FCSR, CC) == 1)
-                                            Fd1 = Fs1;
-                                        if (getFPConditionCode(FCSR, CC+1) == 1)
-                                            Fd2 = Fs2;
+                                        Fd2 = (getCondCode(FCSR, CC) == 1) ?
+                                            Fs1 : Fd1;
+                                        Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
+                                            Fs2 : Fd2;
                                     }});
                                 }
                             }
 
                             format Float64Op {
                                 0x2: movz_ps({{
-                                    if (getFPConditionCode(FCSR, CC) == 0)
-                                        Fd1 = Fs1;
-                                    if (getFPConditionCode(FCSR, CC) == 0)
-                                        Fd2 = Fs2;
+                                    Fd1 = (getCondCode(FCSR, CC) == 0) ?
+                                        Fs1 : Fd1;
+                                    Fd2 = (getCondCode(FCSR, CC) == 0) ?
+                                        Fs2 : Fd2;
                                 }});
-
                                 0x3: movn_ps({{
-                                    if (getFPConditionCode(FCSR, CC) == 1)
-                                        Fd1 = Fs1;
-                                    if (getFPConditionCode(FCSR, CC) == 1)
-                                        Fd2 = Fs2;
+                                    Fd1 = (getCondCode(FCSR, CC) == 1) ?
+                                        Fs1 : Fd1;
+                                    Fd2 = (getCondCode(FCSR, CC) == 1) ?
+                                        Fs2 : Fd2;
                                 }});
                             }
 
                         }
 
                         0x4: decode FUNCTION_LO {
-                            0x0: Float64Op::cvt_s_pu({{
-                                Fd.uw = fpConvert(Fs2.uw, PU_TO_SINGLE);
-                            }});
+                            0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
                         }
 
                         0x5: decode FUNCTION_LO {
-                            format Float64Op {
-                                0x0: cvt_s_pl({{
-                                    Fd.uw = fpConvert(Fs1.uw, PL_TO_SINGLE);
-                                }});
+                            0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
 
-                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft1.uw; }});
-                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft2.uw; }});
-                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft1.uw; }});
-                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft2.uw; }});
+                            format Float64Op {
+                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
+                                                    Ft1.uw;
+                                         }});
+                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
+                                                    Ft2.uw;
+                                         }});
+                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
+                                                    Ft1.uw;
+                                         }});
+                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
+                                                    Ft2.uw;
+                                         }});
                             }
                         }
 
                         0x6: decode FUNCTION_LO {
                             format FloatPSCompareOp {
-                                0x0: c_f_ps({{ cond1 = 0; cond2 = 0; }});
-
-                                0x1: c_un_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = 0;
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = 0;
-
-                                }});
-
-                                0x2: c_eq_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs1.sf == Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf == Ft2.sf);
-                                }});
-
-                                0x3: c_ueq_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs1.sf == Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf == Ft2.sf);
-                                }});
-
-                                0x4: c_olt_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs1.sf < Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf < Ft2.sf);
-                                }});
-
-                                0x5: c_ult_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs.sf < Ft.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf < Ft2.sf);
-                                }});
-
-                                0x6: c_ole_ps({{
-                                    if (isnan(Fs.sf) || isnan(Ft.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs.sf <= Ft.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf <= Ft2.sf);
-                                }});
-
-                                0x7: c_ule_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs1.sf <= Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf <= Ft2.sf);
-                                }});
+                                0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
+                                            UnorderedFalse);
+                                0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
+                                             UnorderedTrue);
+                                0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
+                                             {{ cond2 = (Fs2.sf == Ft2.sf); }},
+                                             UnorderedFalse);
+                                0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
+                                              UnorderedTrue);
+                                0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
+                                              UnorderedFalse);
+                                0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
+                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
+                                              UnorderedTrue);
+                                0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
+                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
+                                              UnorderedFalse);
+                                0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
+                                              UnorderedTrue);
                             }
                         }
 
                         0x7: decode FUNCTION_LO {
-                            format FloatPSCompareWithXcptOp {
-                                0x0: c_sf_ps({{ cond1 = 0; cond2 = 0; }});
-
-                                0x1: c_ngle_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = 0;
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = 0;
-                                  }});
-
-                                0x2: c_seq_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs1.sf == Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf == Ft2.sf);
-                                  }});
-
-                                0x3: c_ngl_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs1.sf == Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf == Ft2.sf);
-                                  }});
-
-                                0x4: c_lt_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs1.sf < Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf < Ft2.sf);
-                                  }});
-
-                                0x5: c_nge_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs1.sf < Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf < Ft2.sf);
-                                  }});
-
-                                0x6: c_le_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 0;
-                                    else
-                                        cond1 = (Fs1.sf <= Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 0;
-                                    else
-                                        cond2 = (Fs2.sf <= Ft2.sf);
-                                  }});
-
-                                0x7: c_ngt_ps({{
-                                    if (isnan(Fs1.sf) || isnan(Ft1.sf))
-                                        cond1 = 1;
-                                    else
-                                        cond1 = (Fs1.sf <= Ft1.sf);
-
-                                    if (isnan(Fs2.sf) || isnan(Ft2.sf))
-                                        cond2 = 1;
-                                    else
-                                        cond2 = (Fs2.sf <= Ft2.sf);
-                                  }});
+                            format FloatPSCompareOp {
+                                0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
+                                             UnorderedFalse, QnanException);
+                                0x1: c_ngle_ps({{ cond1 = 0; }},
+                                               {{ cond2 = 0; }},
+                                               UnorderedTrue, QnanException);
+                                0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
+                                              UnorderedFalse, QnanException);
+                                0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
+                                              UnorderedTrue, QnanException);
+                                0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
+                                             {{ cond2 = (Fs2.sf < Ft2.sf); }},
+                                             UnorderedFalse, QnanException);
+                                0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
+                                              UnorderedTrue, QnanException);
+                                0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
+                                             {{ cond2 = (Fs2.sf <= Ft2.sf); }},
+                                             UnorderedFalse, QnanException);
+                                0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
+                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
+                                              UnorderedTrue, QnanException);
                             }
                         }
                     }
@@ -1209,9 +825,9 @@ decode OPCODE_HI default Unknown::unknown() {
 
         //Table A-19 MIPS32 COP2 Encoding of rs Field
         0x2: decode RS_MSB {
-            0x0: decode RS_HI {
-                0x0: decode RS_LO {
-                    format WarnUnimpl {
+            format FailUnimpl {
+                0x0: decode RS_HI {
+                    0x0: decode RS_LO {
                         0x0: mfc2();
                         0x2: cfc2();
                         0x3: mfhc2();
@@ -1219,18 +835,14 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x6: ctc2();
                         0x7: mftc2();
                     }
-                }
 
-                0x1: decode ND {
-                    0x0: decode TF {
-                        format WarnUnimpl {
+                    0x1: decode ND {
+                        0x0: decode TF {
                             0x0: bc2f();
                             0x1: bc2t();
                         }
-                    }
 
-                    0x1: decode TF {
-                        format WarnUnimpl {
+                        0x1: decode TF {
                             0x0: bc2fl();
                             0x1: bc2tl();
                         }
@@ -1244,441 +856,242 @@ decode OPCODE_HI default Unknown::unknown() {
         //operations are enabled."
         0x3: decode FUNCTION_HI {
             0x0: decode FUNCTION_LO {
-                format LoadFloatMemory {
-                    0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }});
-                    0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }});
-                    0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }});
+                format LoadIndexedMemory {
+                    0x0: lwxc1({{ Fd.uw = Mem.uw;}});
+                    0x1: ldxc1({{ Fd.ud = Mem.ud;}});
+                    0x5: luxc1({{ Fd.ud = Mem.ud;}},
+                               {{ EA = (Rs + Rt) & ~7; }});
                 }
             }
 
             0x1: decode FUNCTION_LO {
-                format StoreFloatMemory {
-                    0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }});
-                    0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
-                    0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
+                format StoreIndexedMemory {
+                    0x0: swxc1({{ Mem.uw = Fs.uw;}});
+                    0x1: sdxc1({{ Mem.ud = Fs.ud;}});
+                    0x5: suxc1({{ Mem.ud = Fs.ud;}},
+                               {{ EA = (Rs + Rt) & ~7; }});
                 }
 
-                0x7: WarnUnimpl::prefx();
+                0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
             }
 
-            format FloatOp {
-                0x3: WarnUnimpl::alnv_ps();
+            0x3: decode FUNCTION_LO {
+                0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
+                                               Fd.ud = Fs.ud;
+                                           } else if (Rs<2:0> == 4) {
+                                             #if BYTE_ORDER == BIG_ENDIAN
+                                               Fd.ud = Fs.ud<31:0> << 32 |
+                                                       Ft.ud<63:32>;
+                                             #elif BYTE_ORDER == LITTLE_ENDIAN
+                                               Fd.ud = Ft.ud<31:0> << 32 |
+                                                       Fs.ud<63:32>;
+                                             #endif
+                                           } else {
+                                               Fd.ud = Fd.ud;
+                                           }
+                                        }});
+            }
 
-                format BasicOp {
-                    0x4: decode FUNCTION_LO {
-                        0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
-                        0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
-                        0x6: madd_ps({{
-                            Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
-                            Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
-                        }});
-                    }
+            format FloatAccOp {
+                0x4: decode FUNCTION_LO {
+                    0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
+                    0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
+                    0x6: madd_ps({{
+                        Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
+                        Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
+                    }});
+                }
 
-                    0x5: decode FUNCTION_LO {
-                        0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
-                        0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
-                        0x6: msub_ps({{
-                            Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
-                            Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
-                        }});
-                    }
+                0x5: decode FUNCTION_LO {
+                    0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
+                    0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
+                    0x6: msub_ps({{
+                        Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
+                        Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
+                    }});
+                }
 
-                    0x6: decode FUNCTION_LO {
-                        0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
-                        0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
-                        0x6: nmadd_ps({{
-                            Fd1.sf = -1 * ((Fs1.df * Ft1.df) + Fr1.df);
-                            Fd2.sf = -1 * ((Fs2.df * Ft2.df) + Fr2.df);
-                        }});
-                    }
+                0x6: decode FUNCTION_LO {
+                    0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
+                    0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
+                    0x6: nmadd_ps({{
+                        Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
+                        Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
+                    }});
+                }
 
-                    0x7: decode FUNCTION_LO {
-                        0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
-                        0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
-                        0x6: nmsub_ps({{
-                            Fd1.sf = -1 * ((Fs1.df * Ft1.df) - Fr1.df);
-                            Fd2.sf = -1 * ((Fs2.df * Ft2.df) - Fr2.df);
-                        }});
-                    }
+                0x7: decode FUNCTION_LO {
+                    0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
+                    0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
+                    0x6: nmsub_ps({{
+                        Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
+                        Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
+                    }});
                 }
+
             }
         }
 
-        format BranchLikely {
-            0x4: beql({{ cond = (Rs.sw == 0); }});
-            0x5: bnel({{ cond = (Rs.sw != 0); }});
-            0x6: blezl({{ cond = (Rs.sw <= 0); }});
-            0x7: bgtzl({{ cond = (Rs.sw > 0); }});
+        format Branch {
+            0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
+            0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
+            0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
+            0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
         }
     }
 
-    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
-
+    0x3: decode OPCODE_LO {
         //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
         0x4: decode FUNCTION_HI {
-
             0x0: decode FUNCTION_LO {
-                format IntOp {
-                    0x0: madd({{
-                        int64_t temp1 = (int64_t) HI << 32 | LO;
-                        temp1 = temp1 + (Rs.sw * Rt.sw);
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
-
-                    0x1: maddu({{
-                        int64_t temp1 = (int64_t) HI << 32 | LO;
-                        temp1 = temp1 + (Rs.uw * Rt.uw);
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
-
-                    0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; 	}});
-
-                    0x4: msub({{
-                        int64_t temp1 = (int64_t) HI << 32 | LO;
-                        temp1 = temp1 - (Rs.sw * Rt.sw);
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
+                0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
+                                   Rd.sw = temp1<31:0>
+                                }});
 
-                    0x5: msubu({{
-                        int64_t temp1 = (int64_t) HI << 32 | LO;
-                        temp1 = temp1 - (Rs.uw * Rt.uw);
-                        HI = temp1<63:32>;
-                        LO = temp1<31:0>;
-                    }});
+                format HiLoOp {
+                    0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
+                                       (Rs.sd * Rt.sd);
+                              }});
+                    0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
+                                        (Rs.ud * Rt.ud);
+                               }});
+                    0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
+                                       (Rs.sd * Rt.sd);
+                              }});
+                    0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
+                                        (Rs.ud * Rt.ud);
+                               }});
                 }
             }
 
             0x4: decode FUNCTION_LO {
                 format BasicOp {
-                    0x0: clz({{
-                        int cnt = 0;
-                        uint32_t mask = 0x80000000;
-                        for (int i=0; i < 32; i++) {
-                            if( (Rs & mask) == 0) {
-                                cnt++;
-                            } else {
-                                break;
-                            }
-                        }
-                        Rd.uw = cnt;
-                    }});
-
-                    0x1: clo({{
-                        int cnt = 0;
-                        uint32_t mask = 0x80000000;
-                        for (int i=0; i < 32; i++) {
-                            if( (Rs & mask) != 0) {
-                                cnt++;
-                            } else {
-                                break;
-                            }
-                        }
-                        Rd.uw = cnt;
-                    }});
+                    0x0: clz({{ int cnt = 32;
+                                for (int idx = 31; idx >= 0; idx--) {
+                                    if( Rs<idx:idx> == 1) {
+                                        cnt = 31 - idx;
+                                        break;
+                                    }
+                                }
+                                Rd.uw = cnt;
+                             }});
+                    0x1: clo({{ int cnt = 32;
+                                for (int idx = 31; idx >= 0; idx--) {
+                                    if( Rs<idx:idx> == 0) {
+                                        cnt = 31 - idx;
+                                        break;
+                                    }
+                                }
+                                Rd.uw = cnt;
+                             }});
                 }
             }
 
             0x7: decode FUNCTION_LO {
-                0x7: WarnUnimpl::sdbbp();
+                0x7: FailUnimpl::sdbbp();
             }
         }
 
-        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
+        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
+        //of the Architecture
         0x7: decode FUNCTION_HI {
-
             0x0: decode FUNCTION_LO {
-                format FailUnimpl {
-                    0x1: ext();
-                    0x4: ins();
+                format BasicOp {
+                    0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
+                    0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
+                                        bits(Rs.uw, MSB-LSB, 0) << LSB |
+                                        bits(Rt.uw, LSB-1, 0);
+                             }});
                 }
             }
 
             0x1: decode FUNCTION_LO {
-                format FailUnimpl {
+                format MipsMT {
                     0x0: fork();
                     0x1: yield();
                 }
             }
 
-
             //Table A-10 MIPS32 BSHFL Encoding of sa Field
             0x4: decode SA {
-
-                0x02: FailUnimpl::wsbh();
-
                 format BasicOp {
-                    0x10: seb({{ Rd.sw = Rt.sw<7:0>}});
-                    0x18: seh({{ Rd.sw = Rt.sw<15:0>}});
+                    0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
+                                          Rt.uw<31:24> << 16 |
+                                          Rt.uw<7:0>   << 8  |
+                                          Rt.uw<15:8>;
+                    }});
+                    0x10: seb({{ Rd.sw = Rt.sb; }});
+                    0x18: seh({{ Rd.sw = Rt.sh; }});
                 }
             }
 
             0x6: decode FUNCTION_LO {
-                0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
+                0x7: FailUnimpl::rdhwr();
             }
         }
     }
 
-    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
+    0x4: decode OPCODE_LO {
         format LoadMemory {
             0x0: lb({{ Rt.sw = Mem.sb; }});
             0x1: lh({{ Rt.sw = Mem.sh; }});
-
-            0x2: lwl({{
-                uint32_t mem_word = Mem.uw;
-                uint32_t unalign_addr = Rs + disp;
-                uint32_t offset = unalign_addr & 0x00000003;
-#if BYTE_ORDER == BIG_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    Rt = mem_word;
-                    break;
-
-                  case 1:
-                    Rt &= 0x000F;
-                    Rt |= (mem_word << 4);
-                    break;
-
-                  case 2:
-                    Rt &= 0x00FF;
-                    Rt |= (mem_word << 8);
-                    break;
-
-                  case 3:
-                    Rt &= 0x0FFF;
-                    Rt |= (mem_word << 12);
-                    break;
-
-                  default:
-                    panic("lwl: bad offset");
-                }
-#elif BYTE_ORDER == LITTLE_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    Rt &= 0x0FFF;
-                    Rt |= (mem_word << 12);
-                    break;
-
-                  case 1:
-                    Rt &= 0x00FF;
-                    Rt |= (mem_word << 8);
-                    break;
-
-                  case 2:
-                    Rt &= 0x000F;
-                    Rt |= (mem_word << 4);
-                    break;
-
-                  case 3:
-                    Rt = mem_word;
-                    break;
-
-                  default:
-                    panic("lwl: bad offset");
-                }
-#endif
-            }}, {{ EA = (Rs + disp) & ~3; }});
-
             0x3: lw({{ Rt.sw = Mem.sw; }});
             0x4: lbu({{ Rt.uw = Mem.ub; }});
             0x5: lhu({{ Rt.uw = Mem.uh; }});
-            0x6: lwr({{
-                uint32_t mem_word = Mem.uw;
-                uint32_t unalign_addr = Rs + disp;
-                uint32_t offset = unalign_addr & 0x00000003;
-
-#if BYTE_ORDER == BIG_ENDIAN
-                switch(offset)
-                {
-                  case 0: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
-                  case 1: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
-                  case 2: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
-                  case 3: Rt = mem_word; break;
-                  default: panic("lwr: bad offset");
-                }
-#elif BYTE_ORDER == LITTLE_ENDIAN
-                switch(offset)
-                {
-                  case 0: Rt = mem_word; break;
-                  case 1: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
-                  case 2: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
-                  case 3: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
-                  default: panic("lwr: bad offset");
-                }
-#endif
-            }},
-            {{ EA = (Rs + disp) & ~3; }});
+        }
+
+        format LoadUnalignedMemory {
+            0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
+                        Rt.uw = mem_word << mem_shift |
+                                Rt.uw & mask(mem_shift);
+                     }});
+            0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
+                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
+                                mem_word >> mem_shift;
+                     }});
         }
     }
 
-    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
+    0x5: decode OPCODE_LO {
         format StoreMemory {
             0x0: sb({{ Mem.ub = Rt<7:0>; }});
             0x1: sh({{ Mem.uh = Rt<15:0>; }});
-            0x2: swl({{
-                uint32_t mem_word = 0;
-                uint32_t aligned_addr = (Rs + disp) & ~3;
-                uint32_t unalign_addr = Rs + disp;
-                uint32_t offset = unalign_addr & 0x00000003;
-
-                DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
-                        aligned_addr,unalign_addr,offset);
-
-                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
-
-#if BYTE_ORDER == BIG_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    Mem = Rt;
-                    break;
-
-                  case 1:
-                    mem_word &= 0xF000;
-                    mem_word |= (Rt >> 4);
-                    Mem = mem_word;
-                    break;
-
-                  case 2:
-                    mem_word &= 0xFF00;
-                    mem_word |= (Rt >> 8);
-                    Mem = mem_word;
-                    break;
-
-                  case 3:
-                    mem_word &= 0xFFF0;
-                    mem_word |= (Rt >> 12);
-                    Mem = mem_word;
-                   break;
-
-                  default:
-                    panic("swl: bad offset");
-                }
-#elif BYTE_ORDER == LITTLE_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    mem_word &= 0xFFF0;
-                    mem_word |= (Rt >> 12);
-                    Mem = mem_word;
-                    break;
-
-                  case 1:
-                    mem_word &= 0xFF00;
-                    mem_word |= (Rt >> 8);
-                    Mem = mem_word;
-                    break;
-
-                  case 2:
-                    mem_word &= 0xF000;
-                    mem_word |= (Rt >> 4);
-                    Mem = mem_word;
-                    break;
-
-                  case 3:
-                    Mem = Rt;
-                   break;
-
-                  default:
-                    panic("swl: bad offset");
-                }
-#endif
-            }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
-
             0x3: sw({{ Mem.uw = Rt<31:0>; }});
-
-            0x6: swr({{
-                uint32_t mem_word = 0;
-                uint32_t aligned_addr = (Rs + disp) & ~3;
-                uint32_t unalign_addr = Rs + disp;
-                uint32_t offset = unalign_addr & 0x00000003;
-
-                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
-
-#if BYTE_ORDER == BIG_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    mem_word &= 0x0FFF;
-                    mem_word |= (Rt << 12);
-                    Mem = mem_word;
-                    break;
-
-                  case 1:
-                    mem_word &= 0x00FF;
-                    mem_word |= (Rt << 8);
-                    Mem = mem_word;
-                    break;
-
-                  case 2:
-                    mem_word &= 0x000F;
-                    mem_word |= (Rt << 4);
-                    Mem = mem_word;
-                    break;
-
-                  case 3:
-                    Mem = Rt;
-                    break;
-
-                  default:
-                    panic("swr: bad offset");
-                }
-#elif BYTE_ORDER == LITTLE_ENDIAN
-                switch(offset)
-                {
-                  case 0:
-                    Mem = Rt;
-                    break;
-
-                  case 1:
-                    mem_word &= 0x000F;
-                    mem_word |= (Rt << 4);
-                    Mem = mem_word;
-                    break;
-
-                  case 2:
-                    mem_word &= 0x00FF;
-                    mem_word |= (Rt << 8);
-                    Mem = mem_word;
-                    break;
-
-                  case 3:
-                    mem_word &= 0x0FFF;
-                    mem_word |= (Rt << 12);
-                    Mem = mem_word;
-                    break;
-
-                  default:
-                    panic("swr: bad offset");
-                }
-#endif
-            }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
         }
 
-        format WarnUnimpl {
-            0x7: cache();
+        format StoreUnalignedMemory {
+            0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
+                        uint32_t mem_shift = 32 - reg_shift;
+                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
+                                   Rt.uw >> reg_shift;
+                     }});
+            0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
+                        mem_word = Rt.uw << reg_shift |
+                                   mem_word & (mask(reg_shift));
+                     }});
         }
 
+        0x7: FailUnimpl::cache();
     }
 
-    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
-        0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED);
-
-        format LoadFloatMemory {
-            0x1: lwc1({{ Ft.uw = Mem.uw;    }});
+    0x6: decode OPCODE_LO {
+        format LoadMemory {
+            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
+            0x1: lwc1({{ Ft.uw = Mem.uw; }});
             0x5: ldc1({{ Ft.ud = Mem.ud; }});
         }
+
+        0x3: Prefetch::pref();
     }
 
 
-    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
-        0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }});
+    0x7: decode OPCODE_LO {
+        0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
+                           {{ uint64_t tmp = write_result;
+                              Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
+                           }}, mem_flags=LOCKED);
 
-        format StoreFloatMemory {
+        format StoreMemory {
             0x1: swc1({{ Mem.uw = Ft.uw; }});
             0x5: sdc1({{ Mem.ud = Ft.ud; }});
         }
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index c02af7ddc..29dafd541 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
         Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
@@ -12,11 +40,11 @@ def template BasicDeclare {{
          */
         class %(class_name)s : public %(base_class)s
         {
-        public:
+          public:
                 /// Constructor.
                 %(class_name)s(MachInst machInst);
                 %(BasicExecDeclare)s
-    };
+        };
 }};
 
 // Basic instruction class constructor template.
@@ -27,6 +55,7 @@ def template BasicConstructor {{
         }
 }};
 
+
 // Basic instruction class execute method template.
 def template BasicExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 8cfa37a20..5230ce9cc 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Control transfer instructions
@@ -68,29 +96,6 @@ output header {{
     };
 
     /**
-     * Base class for branch likely branches (PC-relative control transfers),
-     */
-    class BranchLikely : public PCDependentDisassembly
-    {
-      protected:
-        /// target address (signed) Displacement .
-        int32_t disp;
-
-        /// Constructor.
-        BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : PCDependentDisassembly(mnem, _machInst, __opClass),
-              disp(OFFSET << 2)
-        {
-
-        }
-
-        Addr branchTarget(Addr branchPC) const;
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-
-    /**
      * Base class for jumps (register-indirect control transfers).  In
      * the Mips ISA, these are always unconditional.
      */
@@ -111,7 +116,7 @@ output header {{
         {
         }
 
-        Addr branchTarget(ExecContext *xc) const;
+        Addr branchTarget(ThreadContext *tc) const;
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -126,16 +131,10 @@ output decoder {{
     }
 
     Addr
-    BranchLikely::branchTarget(Addr branchPC) const
-    {
-        return branchPC + 4 + disp;
-    }
-
-    Addr
-    Jump::branchTarget(ExecContext *xc) const
+    Jump::branchTarget(ThreadContext *tc) const
     {
-        Addr NPC = xc->readPC() + 4;
-        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        Addr NPC = tc->readPC() + 4;
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
         return (Rb & ~3) | (NPC & 1);
     }
 
@@ -171,49 +170,12 @@ output decoder {{
         // unconditional branches)
         if (_numSrcRegs == 1) {
             printReg(ss, _srcRegIdx[0]);
-            ss << ",";
+            ss << ", ";
         } else if(_numSrcRegs == 2) {
             printReg(ss, _srcRegIdx[0]);
-            ss << ",";
+            ss << ", ";
             printReg(ss, _srcRegIdx[1]);
-            ss << ",";
-        }
-
-        Addr target = pc + 4 + disp;
-
-        std::string str;
-        if (symtab && symtab->findSymbol(target, str))
-            ss << str;
-        else
-            ccprintf(ss, "0x%x", target);
-
-        string inst_name = mnemonic;
-
-        if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){
-            ccprintf(ss, " (r31=0x%x)",pc+8);
-        }
-
-        return ss.str();
-    }
-
-    std::string
-    BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        std::stringstream ss;
-
-        ccprintf(ss, "%-10s ", mnemonic);
-
-        // There's only one register arg (RA), but it could be
-        // either a source (the condition for conditional
-        // branches) or a destination (the link reg for
-        // unconditional branches)
-        if (_numSrcRegs > 0) {
-            printReg(ss, _srcRegIdx[0]);
-            ss << ",";
-        }
-        else if (_numDestRegs > 0) {
-            printReg(ss, _destRegIdx[0]);
-            ss << ",";
+            ss << ", ";
         }
 
         Addr target = pc + 4 + disp;
@@ -247,72 +209,64 @@ output decoder {{
              printReg(ss, _srcRegIdx[0]);
         } else if(_numSrcRegs == 2) {
             printReg(ss, _srcRegIdx[0]);
-            ss << ",";
+            ss << ", ";
             printReg(ss, _srcRegIdx[1]);
-        } else {
-            panic(">= 3 Source Registers!!!");
         }
 
         return ss.str();
     }
 }};
 
-def format Branch(code,*flags) {{
-    #Add Link Code if Link instruction
-    strlen = len(name)
-    if name[strlen-2:] == 'al':
-        code += 'R31 = NNPC;\n'
+def format Branch(code,*opt_flags) {{
+    not_taken_code = '  NNPC = NNPC;\n'
+    not_taken_code += '} \n'
+
+    #Build Instruction Flags
+    #Use Link & Likely Flags to Add Link/Condition Code
+    inst_flags = ('IsDirectControl', )
+    for x in opt_flags:
+        if x == 'Link':
+            code += 'R31 = NNPC;\n'
+        elif x == 'Likely':
+            not_taken_code = '  NPC = NNPC;\n'
+            not_taken_code += '  NNPC = NNPC + 4;\n'
+            not_taken_code += '} \n'
+            inst_flags = ('IsCondDelaySlot', )
+        else:
+            inst_flags += (x, )
+
+    if 'cond == 1' in code:
+         inst_flags += ('IsCondControl', )
+    else:
+         inst_flags += ('IsUncondControl', )
 
     #Condition code
     code = 'bool cond;\n' + code
     code += 'if (cond) {\n'
     code += '  NNPC = NPC + disp;\n'
     code += '} else {\n'
-    code += '  NNPC = NNPC;\n'
-    code += '} \n'
-
-    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
-                        ('IsDirectControl', 'IsCondControl'))
-
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = BasicExecute.subst(iop)
-}};
-
-
-def format BranchLikely(code,*flags) {{
-    #Add Link Code if Link instruction
-    strlen = len(name)
-    if name[strlen-3:] == 'all':
-        code += 'R31 = NNPC;\n'
-
-    #Condition code
-    code = 'bool cond;\n' + code
-    code += 'if (cond) {'
-    code += 'NNPC = NPC + disp;\n'
-    code += '} \n'
-
-
-    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
-                        ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
+    code += not_taken_code
 
+    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
 
-def format Jump(code,*flags) {{
-    #Add Link Code if Link instruction
-    strlen = len(name)
-    if strlen > 1 and name[1:] == 'al':
+def format Jump(code, *opt_flags) {{
+    #Build Instruction Flags
+    #Use Link Flag to Add Link Code
+    inst_flags = ('IsIndirectControl', 'IsUncondControl')
+    for x in opt_flags:
+        if x == 'Link':
             code = 'R31 = NNPC;\n' + code
+        elif x == 'ClearHazards':
+            code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
+        else:
+            inst_flags += (x, )
 
-
-    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
-                        ('IsIndirectControl', 'IsUncondControl'))
-
+    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
new file mode 100644
index 000000000..6c7d396f3
--- /dev/null
+++ b/src/arch/mips/isa/formats/control.isa
@@ -0,0 +1,156 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+//Outputs to decoder.hh
+output header {{
+
+        class Control : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                           MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+        class CP0Control : public Control
+        {
+                protected:
+
+                /// Constructor
+                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                           Control(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+        class CP1Control : public Control
+        {
+                protected:
+
+                /// Constructor
+                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                           Control(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+        std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            if (mnemonic == "mfc0" || mnemonic == "mtc0") {
+                ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
+            } else {
+
+                // just print the first dest... if there's a second one,
+                // it's generally implicit
+                if (_numDestRegs > 0) {
+                    printReg(ss, _destRegIdx[0]);
+                }
+
+                ss << ", ";
+
+                // just print the first two source regs... if there's
+                // a third one, it's a read-modify-write dest (Rc),
+                // e.g. for CMOVxx
+                if (_numSrcRegs > 0) {
+                    printReg(ss, _srcRegIdx[0]);
+                }
+
+                if (_numSrcRegs > 1) {
+                    ss << ", ";
+                    printReg(ss, _srcRegIdx[1]);
+                }
+            }
+
+            return ss.str();
+        }
+
+        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+            ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
+            return ss.str();
+        }
+
+        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
+            return ss.str();
+        }
+
+}};
+
+def format System(code, *flags) {{
+        iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format CP0Control(code, *flags) {{
+        iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format CP1Control(code, *flags) {{
+        iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+
diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa
index 7d493ffae..4c3eec132 100644
--- a/src/arch/mips/isa/formats/formats.isa
+++ b/src/arch/mips/isa/formats/formats.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 //Templates from this format are used later
 //Include the basic format
 ##include "basic.isa"
@@ -10,8 +38,8 @@
 //Include utility functions
 ##include "util.isa"
 
-//Include the cop0 formats
-##include "cop0.isa"
+//Include the control/cp0/cp1 formats
+##include "control.isa"
 
 //Include the integer formats
 ##include "int.isa"
@@ -22,6 +50,9 @@
 //Include the mem format
 ##include "mem.isa"
 
+//Include the mem format
+##include "mt.isa"
+
 //Include the trap format
 ##include "trap.isa"
 
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 9f2c24755..1e5d62626 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Floating Point operate instructions
@@ -18,49 +46,264 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+                //needs function to check for fpEnable or not
+        };
+
+        class FPCompareOp : public FPOp
+        {
+          protected:
+            FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
+                {
+                }
+
+            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
         };
 }};
 
 output decoder {{
-        std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
-                return "Disassembly of integer instruction\n";
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            ccprintf(ss,"%d",CC);
+
+            if(_numSrcRegs > 0) {
+                ss << ", ";
+                printReg(ss, _srcRegIdx[0]);
+            }
+
+            if(_numSrcRegs > 1) {
+                ss << ", ";
+                printReg(ss, _srcRegIdx[1]);
+            }
+
+            return ss.str();
         }
 }};
 
+output exec {{
 
-// Primary format for float operate instructions:
-def format FloatOp(code, *flags) {{
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
+        //If any operand is Nan return the appropriate QNaN
+        template <class T>
+        bool
+        fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
+                      Trace::InstRecord *traceData)
+        {
+            uint64_t mips_nan = 0;
+            T src_op = 0;
+            int size = sizeof(src_op) * 8;
+
+            for (int i = 0; i < inst->numSrcRegs(); i++) {
+                uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+
+                if (isNan(&src_bits, size) ) {
+                    if (isSnan(&src_bits, size)) {
+                        switch (size)
+                        {
+                          case 32: mips_nan = MIPS32_QNAN; break;
+                          case 64: mips_nan = MIPS64_QNAN; break;
+                          default: panic("Unsupported Floating Point Size (%d)", size);
+                        }
+                    } else {
+                        mips_nan = src_bits;
+                    }
+
+                    xc->setFloatRegBits(inst, 0, mips_nan, size);
+                    if (traceData) { traceData->setData(mips_nan); }
+                    return true;
+                }
+            }
+            return false;
+        }
+
+        template <class T>
+        bool
+        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
+                    Trace::InstRecord *traceData)
+        {
+            uint64_t mips_nan = 0;
+            T src_op = dest_val;
+            int size = sizeof(src_op) * 8;
+
+            if (isNan(&src_op, size)) {
+                switch (size)
+                {
+                  case 32: mips_nan = MIPS32_QNAN; break;
+                  case 64: mips_nan = MIPS64_QNAN; break;
+                  default: panic("Unsupported Floating Point Size (%d)", size);
+                }
+
+                //Set value to QNAN
+                cpu->setFloatRegBits(inst, 0, mips_nan, size);
+
+                //Read FCSR from FloatRegFile
+                uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
+
+                //Write FCSR from FloatRegFile
+                cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+
+                if (traceData) { traceData->setData(mips_nan); }
+                return true;
+            }
+
+            return false;
+        }
+
+        void
+        fpResetCauseBits(%(CPU_exec_context)s *cpu)
+        {
+            //Read FCSR from FloatRegFile
+            uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
+
+            fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
+
+            //Write FCSR from FloatRegFile
+            cpu->tc->setFloatRegBits(FCSR, fcsr);
+        }
 }};
 
-def format FloatCompareOp(code, *flags) {{
-        code = 'bool cond;\n' + code
-        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
+def template FloatingPointExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = NoFault;
+
+                %(fp_enable_check)s;
+
+                //When is the right time to reset cause bits?
+                //start of every instruction or every cycle?
+                fpResetCauseBits(xc);
+
+                %(op_decl)s;
+                %(op_rd)s;
+
+                //Check if any FP operand is a NaN value
+                if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
+                    %(code)s;
+
+                    //Change this code for Full-System/Sycall Emulation
+                    //separation
+                    //----
+                    //Should Full System-Mode throw a fault here?
+                    //----
+                    //Check for IEEE 754 FP Exceptions
+                    //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
+                    if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+                        fault == NoFault)
+                    {
+                        %(op_wb)s;
+                    }
+                }
+
+                return fault;
+        }
 }};
 
-def format FloatCompareWithXcptOp(code, *flags) {{
-        code = 'bool cond;\n' + code
-        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+// Primary format for float point operate instructions:
+def format FloatOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
+        exec_output = FloatingPointExecute.subst(iop)
+}};
+
+def format FloatCompareOp(cond_code, *flags) {{
+    import sys
+
+    code = 'bool cond;\n'
+    if '.sf' in cond_code or 'SinglePrecision' in flags:
+        if 'QnanException' in flags:
+            code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
+            code += '\tFCSR = genInvalidVector(FCSR);\n'
+            code += '\treturn NoFault;'
+            code += '}\n else '
+        code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
+    elif '.df' in cond_code or 'DoublePrecision' in flags:
+        if 'QnanException' in flags:
+            code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
+            code += '\tFCSR = genInvalidVector(FCSR);\n'
+            code += '\treturn NoFault;'
+            code += '}\n else '
+        code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
+    else:
+       sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
+
+    if 'UnorderedTrue' in flags:
+       code += 'cond = 1;\n'
+    elif 'UnorderedFalse' in flags:
+       code += 'cond = 0;\n'
+    else:
+       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+
+    code += '} else {\n'
+    code +=  cond_code + '}'
+    code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
+
+    iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
 }};
 
 def format FloatConvertOp(code, *flags) {{
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+    import sys
+
+    #Determine Source Type
+    convert = 'fpConvert('
+    if '.sf' in code:
+        code = 'float ' + code + '\n'
+        convert += 'SINGLE_TO_'
+    elif '.df' in code:
+        code = 'double ' + code + '\n'
+        convert += 'DOUBLE_TO_'
+    elif '.uw' in code:
+        code = 'uint32_t ' + code + '\n'
+        convert += 'WORD_TO_'
+    elif '.ud' in code:
+        code = 'uint64_t ' + code + '\n'
+        convert += 'LONG_TO_'
+    else:
+        sys.exit("Error Determining Source Type for Conversion")
+
+    #Determine Destination Type
+    if 'ToSingle' in flags:
+        code += 'Fd.uw = ' + convert + 'SINGLE, '
+    elif 'ToDouble' in flags:
+        code += 'Fd.ud = ' + convert + 'DOUBLE, '
+    elif 'ToWord' in flags:
+        code += 'Fd.uw = ' + convert + 'WORD, '
+    elif 'ToLong' in flags:
+        code += 'Fd.ud = ' + convert + 'LONG, '
+    else:
+        sys.exit("Error Determining Destination Type for Conversion")
+
+    #Figure out how to round value
+    if 'Ceil' in flags:
+        code += 'ceil(val)); '
+    elif 'Floor' in flags:
+        code += 'floor(val)); '
+    elif 'Round' in flags:
+        code += 'roundFP(val, 0)); '
+    elif 'Trunc' in flags:
+        code += 'truncFP(val));'
+    else:
+        code += 'val); '
+
+    iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatAccOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
@@ -76,34 +319,51 @@ def format Float64Op(code, *flags) {{
         exec_output = BasicExecute.subst(iop)
 }};
 
-def format Float64ConvertOp(code, *flags) {{
-        code = 'bool cond;\n' + code
-        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
-}};
+def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
+    import sys
 
-def format FloatPSCompareOp(code, *flags) {{
-        code = 'bool cond1;\nbool cond2;\n' + code
-        code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
-        code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
-}};
+    code = 'bool cond1, cond2;\n'
+    code += 'bool code_block1, code_block2;\n'
+    code += 'code_block1 = code_block2 = true;\n'
 
-def format FloatPSCompareWithXcptOp(code, *flags) {{
-        code = 'bool cond1;\nbool cond2;\n' + code
-        code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
-        code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
+    if 'QnanException' in flags:
+        code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
+        code += '\tFCSR = genInvalidVector(FCSR);\n'
+        code += 'code_block1 = false;'
+        code += '}\n'
+        code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
+        code += '\tFCSR = genInvalidVector(FCSR);\n'
+        code += 'code_block2 = false;'
+        code += '}\n'
+
+    code += 'if (code_block1) {'
+    code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
+    if 'UnorderedTrue' in flags:
+       code += 'cond1 = 1;\n'
+    elif 'UnorderedFalse' in flags:
+       code += 'cond1 = 0;\n'
+    else:
+       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+    code += '} else {\n'
+    code +=  cond_code1
+    code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
+
+    code += 'if (code_block2) {'
+    code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
+    if 'UnorderedTrue' in flags:
+       code += 'cond2 = 1;\n'
+    elif 'UnorderedFalse' in flags:
+       code += 'cond2 = 0;\n'
+    else:
+       sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+    code += '} else {\n'
+    code +=  cond_code2
+    code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
+
+    iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
 }};
+
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 7d38b9ff5..56a4ec204 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -1,11 +1,37 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Integer operate instructions
 //
-
-//Outputs to decoder.hh
 output header {{
 #include <iostream>
     using namespace std;
@@ -25,6 +51,34 @@ output header {{
                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
         };
 
+
+        class HiLoOp: public IntOp
+        {
+                protected:
+
+                /// Constructor
+                HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                                IntOp(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+        class HiLoMiscOp: public HiLoOp
+        {
+                protected:
+
+                /// Constructor
+                HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                                HiLoOp(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+
         class IntImmOp : public MipsStaticInst
         {
                 protected:
@@ -52,6 +106,33 @@ output header {{
 
 }};
 
+// HiLo<Misc> instruction class execute method template.
+// Mainly to get instruction trace data to print out
+// correctly
+def template HiLoExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = NoFault;
+
+                %(fp_enable_check)s;
+                %(op_decl)s;
+                %(op_rd)s;
+                %(code)s;
+
+                if(fault == NoFault)
+                {
+                    %(op_wb)s;
+                    //If there are 2 Destination Registers then
+                    //concatenate the values for the traceData
+                    if(traceData && _numDestRegs == 2) {
+                        uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
+                        traceData->setData(hilo_final_val);
+                    }
+                }
+                return fault;
+        }
+}};
+
 //Outputs to decoder.cc
 output decoder {{
         std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -64,7 +145,7 @@ output decoder {{
             // it's generally implicit
             if (_numDestRegs > 0) {
                 printReg(ss, _destRegIdx[0]);
-                ss << ",";
+                ss << ", ";
             }
 
             // just print the first two source regs... if there's
@@ -75,13 +156,47 @@ output decoder {{
             }
 
             if (_numSrcRegs > 1) {
-                ss << ",";
+                ss << ", ";
+                printReg(ss, _srcRegIdx[1]);
+            }
+
+            return ss.str();
+        }
+
+        std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            //Destination Registers are implicit for HI/LO ops
+            if (_numSrcRegs > 0) {
+                printReg(ss, _srcRegIdx[0]);
+            }
+
+            if (_numSrcRegs > 1) {
+                ss << ", ";
                 printReg(ss, _srcRegIdx[1]);
             }
 
             return ss.str();
         }
 
+        std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+                printReg(ss, _destRegIdx[0]);
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+                printReg(ss, _srcRegIdx[0]);
+            }
+
+            return ss.str();
+        }
+
         std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream ss;
@@ -92,15 +207,15 @@ output decoder {{
                 printReg(ss, _destRegIdx[0]);
             }
 
-            ss << ",";
+            ss << ", ";
 
             if (_numSrcRegs > 0) {
                 printReg(ss, _srcRegIdx[0]);
-                ss << ",";
+                ss << ", ";
             }
 
             if( mnemonic == "lui")
-                ccprintf(ss, "%08p ", sextImm);
+                ccprintf(ss, "0x%x ", sextImm);
             else
                 ss << (int) sextImm;
 
@@ -109,23 +224,47 @@ output decoder {{
 
 }};
 
-//Used by decoder.isa
 def format IntOp(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-
-        # Figure out if we are creating a IntImmOp or a IntOp
-        # by looking at the instruction name
-        iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
-        strlen = len(name)
-        if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
-            iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
-
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = OperateNopCheckDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
+    iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = RegNopCheckDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format IntImmOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = ImmNopCheckDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format HiLoOp(code, *opt_flags) {{
+    if '.sd' in code:
+        code = 'int64_t ' + code
+    elif '.ud' in code:
+        code = 'uint64_t ' + code
+
+    code += 'HI = val<63:32>;\n'
+    code += 'LO = val<31:0>;\n'
+
+    iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = HiLoExecute.subst(iop)
 }};
 
+def format HiLoMiscOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = HiLoExecute.subst(iop)
+}};
+
+
+
 
 
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index e2afc7252..f03f7becd 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -25,6 +25,14 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+//          Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory-format instructions
+//
 
 output header {{
     /**
@@ -50,14 +58,8 @@ output header {{
                StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : MipsStaticInst(mnem, _machInst, __opClass),
               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
-              disp(OFFSET)
+              disp(sext<16>(OFFSET))
         {
-            //If Bit 15 is 1 then Sign Extend
-            int32_t temp = disp & 0x00008000;
-
-            if (temp > 0) {
-                disp |= 0xFFFF0000;
-            }
         }
 
         std::string
@@ -69,6 +71,24 @@ output header {{
         const StaticInstPtr &memAccInst() const { return memAccPtr; }
     };
 
+     /**
+     * Base class for a few miscellaneous memory-format insts
+     * that don't interpret the disp field
+     */
+    class MemoryNoDisp : public Memory
+    {
+      protected:
+        /// Constructor
+        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
+            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
+        {
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 }};
 
 
@@ -76,21 +96,20 @@ output decoder {{
     std::string
     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
-        return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
+        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
                         flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
     }
 
+    std::string
+    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
+                        flags[IsFloating] ? 'f' : 'r',
+                        flags[IsFloating] ? FD : RD,
+                        RS, RT);
+    }
 }};
 
-def format LoadAddress(code) {{
-    iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = BasicExecute.subst(iop)
-}};
-
-
 def template LoadStoreDeclare {{
     /**
      * Static instruction class for "%(mnemonic)s".
@@ -418,27 +437,76 @@ def template StoreCompleteAcc {{
     }
 }};
 
-// load instructions use Rt as dest, so check for
-// Rt == 31 to detect nops
-def template LoadNopCheckDecode {{
- {
-     MipsStaticInst *i = new %(class_name)s(machInst);
-     if (RT == 0) {
-         i = makeNop(i);
-     }
-     return i;
- }
+
+def template MiscMemAccExecute {{
+    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+                                          Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        EA = xc->getEA();
+
+        if (fault == NoFault) {
+            %(code)s;
+        }
+
+        return NoFault;
+    }
+}};
+
+def template MiscExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                                  Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        return NoFault;
+    }
+}};
+
+def template MiscInitiateAcc {{
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        panic("Misc instruction does not support split access method!");
+        return NoFault;
+    }
+}};
+
+
+def template MiscCompleteAcc {{
+    Fault %(class_name)s::completeAcc(uint8_t *data,
+                                      %(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        panic("Misc instruction does not support split access method!");
+
+        return NoFault;
+    }
 }};
 
 def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
+                      decode_template = ImmNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
-
 def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
@@ -446,26 +514,69 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                       exec_template_base = 'Store')
 }};
 
-//FP loads are offloaded to these formats for now ...
-def format LoadFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = BasicDecode,
+                      decode_template = ImmNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
+def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+                     mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      exec_template_base = 'Store')
+}};
+
+def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
+                     mem_flags = [], inst_flags = []) {{
+    decl_code = 'uint32_t mem_word = Mem.uw;\n'
+    decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
+    decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
+    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
+    decl_code += '\tbyte_offset ^= 3;\n'
+    decl_code += '#endif\n'
+
+    memacc_code = decl_code + memacc_code
+
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      decode_template = ImmNopCheckDecode,
+                      exec_template_base = 'Load')
+}};
 
-def format StoreFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
                      mem_flags = [], inst_flags = []) {{
+    decl_code = 'uint32_t mem_word = 0;\n'
+    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
+    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
+    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
+    decl_code += '\tbyte_offset ^= 3;\n'
+    decl_code += '#endif\n'
+    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
+    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
+
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       exec_template_base = 'Store')
 }};
 
+def format Prefetch(ea_code = {{ EA = Rs + disp; }},
+                          mem_flags = [], pf_flags = [], inst_flags = []) {{
+    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
+                                  'IsDataPrefetch', 'MemReadOp']
+
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code,
+                      'xc->prefetch(EA, memAccessFlags);',
+                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
+
+}};
 
-def format UnalignedStore(memacc_code, postacc_code,
-                     ea_code = {{ EA = Rb + disp; }},
+def format StoreCond(memacc_code, postacc_code,
+                     ea_code = {{ EA = Rs + disp; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
new file mode 100644
index 000000000..96435f8c9
--- /dev/null
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -0,0 +1,82 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// MT instructions
+//
+
+output header {{
+        /**
+         * Base class for MIPS MT ASE operations.
+         */
+        class MT : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                MT(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                    MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        //Edit This Template When MT is Implemented
+        std::string MT::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of MT instruction\n";
+        }
+}};
+
+def template MTExecute {{
+        //Edit This Template When MT is Implemented
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                //Call into the trap handler with the appropriate fault
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format MipsMT() {{
+        code = 'panic(\"Mips MT Is Currently Unimplemented.\");\n'
+        iop = InstObjParams(name, Name, 'MT', CodeBlock(code))
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 2aa4816e3..7f3d313ad 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Nop
@@ -36,11 +64,7 @@ output decoder {{
     std::string Nop::generateDisassembly(Addr pc,
                                          const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return originalDisassembly;
-#else
-        return csprintf("%-10s (%s)", "nop", originalDisassembly);
-#endif
+        return csprintf("%-10s %s", "nop", originalDisassembly);
     }
 
     /// Helper function for decoding nops.  Substitute Nop object
@@ -49,7 +73,8 @@ output decoder {{
     MipsStaticInst *
     makeNop(MipsStaticInst *inst)
     {
-        MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        std::string nop_str = "(" + inst->disassemble(0) + ")";
+        MipsStaticInst *nop = new Nop(nop_str, inst->machInst);
         delete inst;
         return nop;
     }
@@ -63,16 +88,36 @@ output exec {{
     }
 }};
 
-// integer & FP operate instructions use RT as dest, so check for
-// RT == 0 to detect nops
-def template OperateNopCheckDecode {{
+// Int & FP operate instructions use RD as dest, so check for
+// RD == 0 to detect nops
+def template RegNopCheckDecode {{
  {
      MipsStaticInst *i = new %(class_name)s(machInst);
+     //if (RD == 0) {
+         //i = makeNop(i);
+         //}
+     return i;
+ }
+}};
 
+def template OperateNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
      //if (RD == 0) {
-     //  i = makeNop(i);
+     // i = makeNop(i);
      //}
+     return i;
+ }
+}};
 
+// IntImm & Memory  instructions use Rt as dest, so check for
+// Rt == 0 to detect nops
+def template ImmNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
+     //if (RT == 0) {
+     // i = makeNop(i);
+     // }
      return i;
  }
 }};
@@ -89,6 +134,6 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
 }};
 
 def format Nop() {{
-        decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n'
+        decode_block = 'return new Nop(\"\",machInst);\n'
 }};
 
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index f5e4076f2..b974ccbed 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -1,3 +1,33 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // TlbOp instructions
@@ -30,13 +60,10 @@ output decoder {{
 def template TlbOpExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
-                //Call into the trap handler with the appropriate fault
-                return No_Fault;
-        }
-
                 //Write the resulting state to the execution context
                 %(op_wb)s;
 
+                //Call into the trap handler with the appropriate fault
                 return No_Fault;
         }
 }};
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 6884d4fa8..b9066f374 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -1,3 +1,33 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Trap instructions
@@ -23,27 +53,26 @@ output header {{
 output decoder {{
         std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
-                return "Disassembly of integer instruction\n";
+                return "Disassembly of trap instruction\n";
         }
 }};
 
 def template TrapExecute {{
+        //Edit This Template When Traps Are Implemented
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
-                //Call into the trap handler with the appropriate fault
-                return No_Fault;
-        }
-
                 //Write the resulting state to the execution context
                 %(op_wb)s;
 
+                //Call into the trap handler with the appropriate fault
                 return No_Fault;
         }
 }};
 
-// Primary format for integer operate instructions:
 def format Trap(code, *flags) {{
-        code = 'bool cond;\n' + code;
+        code = 'warn(\"'
+        code += 'Trap Exception Handler Is Currently Not Implemented.'
+        code += '\");'
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 475a88752..03068fa74 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -1,6 +1,7 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+
+// Copyright (c) 2006 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -25,6 +26,13 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// Unimplemented instructions
+//
 
 output header {{
     /**
@@ -96,11 +104,7 @@ output decoder {{
     WarnUnimplemented::generateDisassembly(Addr pc,
                                            const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return csprintf("%-10s", mnemonic);
-#else
         return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
     }
 }};
 
@@ -120,7 +124,7 @@ output exec {{
                                Trace::InstRecord *traceData) const
     {
         if (!warned) {
-            warn("instruction '%s' unimplemented\n", mnemonic);
+            warn("\tinstruction '%s' unimplemented\n", mnemonic);
             warned = true;
         }
 
@@ -139,28 +143,3 @@ def format WarnUnimpl() {{
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
 
-output header {{
-    /**
-     * Static instruction class for unknown (illegal) instructions.
-     * These cause simulator termination if they are executed in a
-     * non-speculative mode.  This is a leaf class.
-     */
-    class Unknown : public MipsStaticInst
-    {
-      public:
-        /// Constructor
-        Unknown(MachInst _machInst)
-            : MipsStaticInst("unknown", _machInst, No_OpClass)
-        {
-            // don't call execute() (which panics) if we're on a
-            // speculative path
-            flags[IsNonSpeculative] = true;
-        }
-
-        %(BasicExecDeclare)s
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-}};
-
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index ba83c007e..70b3901e9 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -25,30 +25,40 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
-output header {{
-        std::string inst2string(MachInst machInst);
-}};
-output decoder {{
-
-std::string inst2string(MachInst machInst)
-{
-    string str = "";
-    uint32_t mask = 0x80000000;
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
 
-    for(int i=0; i < 32; i++) {
-        if ((machInst & mask) == 0) {
-            str += "0";
-        } else {
-            str += "1";
+output header {{
+    /**
+     * Static instruction class for unknown (illegal) instructions.
+     * These cause simulator termination if they are executed in a
+     * non-speculative mode.  This is a leaf class.
+     */
+    class Unknown : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        Unknown(MachInst _machInst)
+            : MipsStaticInst("unknown", _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
         }
 
-        mask = mask >> 1;
-    }
+        %(BasicExecDeclare)s
 
-    return str;
-}
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
 
+output decoder {{
     std::string
     Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 615160931..0cc375af3 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -1,5 +1,34 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+//          Korey Sewell
+
 let {{
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                   postacc_code = '', base_class = 'Memory',
@@ -90,7 +119,31 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
             + completeAccTemplate.subst(completeacc_iop))
 }};
 
+output header {{
+        std::string inst2string(MachInst machInst);
+}};
+
+output decoder {{
+
+std::string inst2string(MachInst machInst)
+{
+    string str = "";
+    uint32_t mask = 0x80000000;
+
+    for(int i=0; i < 32; i++) {
+        if ((machInst & mask) == 0) {
+            str += "0";
+        } else {
+            str += "1";
+        }
 
+        mask = mask >> 1;
+    }
+
+    return str;
+}
+
+}};
 output exec {{
 
     using namespace MipsISA;
@@ -124,6 +177,7 @@ output exec {{
 #endif
 
 
+
 }};
 
 
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 9c370fbe3..6b5f3c588 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -1,3 +1,33 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Output include file directives.
@@ -16,9 +46,10 @@ output decoder {{
 #include "arch/mips/isa_traits.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+#include "cpu/thread_context.hh"
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
 
 #include <math.h>
 #if defined(linux)
@@ -31,6 +62,8 @@ using namespace MipsISA;
 output exec {{
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
+
 #include <math.h>
 #if defined(linux)
 #include <fenv.h>
diff --git a/src/arch/mips/isa/main.isa b/src/arch/mips/isa/main.isa
index 01d81323e..2d7c63cd5 100644
--- a/src/arch/mips/isa/main.isa
+++ b/src/arch/mips/isa/main.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -25,7 +25,16 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// MIPS ISA description file.
+//
+////////////////////////////////////////////////////////////////////
 
+//Include the C++ include directives
 ##include "includes.isa"
 
 ////////////////////////////////////////////////////////////////////
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 0f9c74b48..3843dc053 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -1,3 +1,33 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 def operand_types {{
     'sb' : ('signed int', 8),
     'ub' : ('unsigned int', 8),
@@ -23,8 +53,8 @@ def operands {{
     'R2':  ('IntReg', 'uw','2', 'IsInteger', 5),
 
     #Special Integer Reg operands
-    'HI':  ('IntReg', 'uw','32', 'IsInteger', 6),
-    'LO':  ('IntReg', 'uw','33', 'IsInteger', 7),
+    'HI':  ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
+    'LO':  ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
 
     #Immediate Value operand
     'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
@@ -36,11 +66,11 @@ def operands {{
     'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
 
     #Special Floating Point Control Reg Operands
-    'FIR':  ('FloatReg', 'uw', '32', 'IsFloating', 1),
-    'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2),
-    'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3),
-    'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3),
-    'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3),
+    'FIR':  ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
+    'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
+    'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
+    'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
+    'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
 
      #Operands For Paired Singles FP Operations
     'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
index 216a6e2ec..85acc4e8c 100644
--- a/src/arch/mips/isa_traits.cc
+++ b/src/arch/mips/isa_traits.cc
@@ -24,10 +24,13 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Korey Sewell
  */
 
 #include "arch/mips/isa_traits.hh"
-#include "config/full_system.hh"
+//#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/serialize.hh"
 #include "base/bitfield.hh"
@@ -37,111 +40,17 @@ using namespace std;
 
 
 void
-MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
-    /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
-    uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
-    lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
-    lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
-
-#if FULL_SYSTEM
-    copyIprs(xc);
-    #endif*/
+    panic("Copy Regs Not Implemented Yet\n");
 }
 
 void
-MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
-{
-    /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
-    uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
-    lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
-    lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
-
-    #endif*/
-}
-
-uint64_t
-MipsISA::fpConvert(double fp_val, ConvertType cvt_type)
-{
-
-    switch (cvt_type)
-    {
-      case SINGLE_TO_DOUBLE:
-        double sdouble_val = fp_val;
-        void  *sdouble_ptr = &sdouble_val;
-        uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
-        return sdp_bits;
-
-      case SINGLE_TO_WORD:
-        int32_t sword_val  = (int32_t) fp_val;
-        void  *sword_ptr   = &sword_val;
-        uint64_t sword_bits= *(uint32_t *) sword_ptr;
-        return sword_bits;
-
-      case WORD_TO_SINGLE:
-        float wfloat_val   = fp_val;
-        void  *wfloat_ptr  = &wfloat_val;
-        uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
-        return wfloat_bits;
-
-      case WORD_TO_DOUBLE:
-        double wdouble_val = fp_val;
-        void  *wdouble_ptr = &wdouble_val;
-        uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
-        return wdp_bits;
-
-      default:
-        panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
-        return 0;
-    }
-}
-
-double
-MipsISA::roundFP(double val, int digits)
-{
-    double digit_offset = pow(10.0,digits);
-    val = val * digit_offset;
-    val = val + 0.5;
-    val = floor(val);
-    val = val / digit_offset;
-    return val;
-}
-
-double
-MipsISA::truncFP(double val)
-{
-    int trunc_val = (int) val;
-    return (double) trunc_val;
-}
-
-bool
-MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc)
+MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
 {
-    //uint32_t cc_bits = xc->readFloatReg(35);
-    return false;//regFile.floatRegfile.getConditionCode(cc);
-}
-
-uint32_t
-MipsISA::makeCCVector(uint32_t fcsr, int num, bool val)
-{
-    int shift = (num == 0) ? 22 : num + 23;
-
-    fcsr = fcsr | (val << shift);
-
-    return fcsr;
+    panic("Copy Misc. Regs Not Implemented Yet\n");
 }
 
-#if FULL_SYSTEM
-
-static inline Addr
-TruncPage(Addr addr)
-{ return addr & ~(MipsISA::PageBytes - 1); }
-
-static inline Addr
-RoundPage(Addr addr)
-{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
-#endif
-
 void
 IntRegFile::serialize(std::ostream &os)
 {
@@ -166,12 +75,6 @@ RegFile::serialize(std::ostream &os)
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
-#if FULL_SYSTEM
-    SERIALIZE_ARRAY(palregs, NumIntRegs);
-    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-    SERIALIZE_SCALAR(intrflag);
-    SERIALIZE_SCALAR(pal_shadow);
-#endif
 }
 
 
@@ -187,43 +90,5 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
-#if FULL_SYSTEM
-    UNSERIALIZE_ARRAY(palregs, NumIntRegs);
-    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-    UNSERIALIZE_SCALAR(intrflag);
-    UNSERIALIZE_SCALAR(pal_shadow);
-#endif
-}
 
-
-#if FULL_SYSTEM
-void
-PTE::serialize(std::ostream &os)
-{
-    SERIALIZE_SCALAR(tag);
-    SERIALIZE_SCALAR(ppn);
-    SERIALIZE_SCALAR(xre);
-    SERIALIZE_SCALAR(xwe);
-    SERIALIZE_SCALAR(asn);
-    SERIALIZE_SCALAR(asma);
-    SERIALIZE_SCALAR(fonr);
-    SERIALIZE_SCALAR(fonw);
-    SERIALIZE_SCALAR(valid);
 }
-
-
-void
-PTE::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_SCALAR(tag);
-    UNSERIALIZE_SCALAR(ppn);
-    UNSERIALIZE_SCALAR(xre);
-    UNSERIALIZE_SCALAR(xwe);
-    UNSERIALIZE_SCALAR(asn);
-    UNSERIALIZE_SCALAR(asma);
-    UNSERIALIZE_SCALAR(fonr);
-    UNSERIALIZE_SCALAR(fonw);
-    UNSERIALIZE_SCALAR(valid);
-}
-
-#endif //FULL_SYSTEM
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 148c405df..ff994bef9 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
@@ -45,7 +48,7 @@
 class FastCPU;
 class FullCPU;
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 
 namespace LittleEndianGuest {};
 
@@ -54,12 +57,6 @@ namespace LittleEndianGuest {};
 class StaticInst;
 class StaticInstPtr;
 
-namespace MIPS34K {
-int DTB_ASN_ASN(uint64_t reg);
-int ITB_ASN_ASN(uint64_t reg);
-};
-
-#if !FULL_SYSTEM
 class SyscallReturn {
         public:
            template <class T>
@@ -92,7 +89,6 @@ class SyscallReturn {
            uint64_t retval;
            bool success;
 };
-#endif
 
 namespace MipsISA
 {
@@ -128,20 +124,14 @@ namespace MipsISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
 
     const Addr MaxAddr = (Addr)-1;
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
-
-    uint64_t fpConvert(double fp_val, ConvertType cvt_type);
-    double roundFP(double val, int digits);
-    double truncFP(double val);
-    bool getFPConditionCode(uint32_t fcsr_reg, int cc);
-    uint32_t makeCCVector(uint32_t fcsr, int num, bool val);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     // Machine operations
 
@@ -188,12 +178,6 @@ namespace MipsISA
 
 };
 
-#if FULL_SYSTEM
-
-#include "arch/mips/mips34k.hh"
-
-#endif
-
 using namespace MipsISA;
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index ffc5da2e1..17e735527 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #include "arch/mips/linux/linux.hh"
@@ -31,7 +33,7 @@
 #include "arch/mips/isa_traits.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"
 
 #include "sim/process.hh"
@@ -43,9 +45,9 @@ using namespace MipsISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -53,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "mips");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
     return 0;
 }
 
@@ -62,18 +64,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
 /// different in practice from those used by Tru64 processes.
 static SyscallReturn
 sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 45: { // GSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(xc->getMemPort());
+          fpcr.copyOut(tc->getMemPort());
           return 0;
       }
 
@@ -89,17 +91,17 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
 /// Target sys_setsysinfo() handler.
 static SyscallReturn
 sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 14: { // SSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(xc->getMemPort());
+          fpcr.copyIn(tc->getMemPort());
           DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
@@ -133,7 +135,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 14 */ SyscallDesc("mknod", unimplementedFunc),
     /* 15 */ SyscallDesc("chmod", chmodFunc<MipsLinux>),
     /* 16 */ SyscallDesc("lchown", chownFunc),
-    /* 17 */ SyscallDesc("break", obreakFunc), /*obreak*/
+    /* 17 */ SyscallDesc("break", obreakFunc),
     /* 18 */ SyscallDesc("unused#18", unimplementedFunc),
     /* 19 */ SyscallDesc("lseek", lseekFunc),
     /* 20 */ SyscallDesc("getpid", getpidFunc),
@@ -161,7 +163,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 42 */ SyscallDesc("pipe", unimplementedFunc),
     /* 43 */ SyscallDesc("times", unimplementedFunc),
     /* 44 */ SyscallDesc("prof", unimplementedFunc),
-    /* 45 */ SyscallDesc("brk", obreakFunc),/*openFunc<MipsLinux>*/
+    /* 45 */ SyscallDesc("brk", obreakFunc),
     /* 46 */ SyscallDesc("setgid", unimplementedFunc),
     /* 47 */ SyscallDesc("getgid", getgidFunc),
     /* 48 */ SyscallDesc("signal", ignoreFunc),
@@ -171,7 +173,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 52 */ SyscallDesc("umount2", unimplementedFunc),
     /* 53 */ SyscallDesc("lock", unimplementedFunc),
     /* 54 */ SyscallDesc("ioctl", ioctlFunc<MipsLinux>),
-    /* 55 */ SyscallDesc("fcntl", unimplementedFunc),
+    /* 55 */ SyscallDesc("fcntl", fcntlFunc),
     /* 56 */ SyscallDesc("mpx", unimplementedFunc),
     /* 57 */ SyscallDesc("setpgid", unimplementedFunc),
     /* 58 */ SyscallDesc("ulimit", unimplementedFunc),
@@ -208,8 +210,8 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 89 */ SyscallDesc("readdir", unimplementedFunc),
     /* 90 */ SyscallDesc("mmap", mmapFunc<MipsLinux>),
     /* 91 */ SyscallDesc("munmap",munmapFunc),
-    /* 92 */ SyscallDesc("truncate", fcntlFunc),
-    /* 93 */ SyscallDesc("ftruncate", unimplementedFunc),
+    /* 92 */ SyscallDesc("truncate", truncateFunc),
+    /* 93 */ SyscallDesc("ftruncate", ftruncateFunc),
     /* 94 */ SyscallDesc("fchmod", unimplementedFunc),
     /* 95 */ SyscallDesc("fchown", unimplementedFunc),
     /* 96 */ SyscallDesc("getpriority", unimplementedFunc),
@@ -260,7 +262,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 141 */ SyscallDesc("getdents", unimplementedFunc),
     /* 142 */ SyscallDesc("newselect", unimplementedFunc),
     /* 143 */ SyscallDesc("flock", unimplementedFunc),
-    /* 144 */ SyscallDesc("msync", unimplementedFunc),/*getrlimitFunc<MipsLinux>*/
+    /* 144 */ SyscallDesc("msync", unimplementedFunc),
     /* 145 */ SyscallDesc("readv", unimplementedFunc),
     /* 146 */ SyscallDesc("writev", writevFunc<MipsLinux>),
     /* 147 */ SyscallDesc("cacheflush", unimplementedFunc),
@@ -336,7 +338,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 217 */ SyscallDesc("mincore", unimplementedFunc),
     /* 218 */ SyscallDesc("madvise", unimplementedFunc),
     /* 219 */ SyscallDesc("getdents64", unimplementedFunc),
-    /* 220 */ SyscallDesc("fcntl64", fcntlFunc),
+    /* 220 */ SyscallDesc("fcntl64", fcntl64Func),
     /* 221 */ SyscallDesc("reserved#221", unimplementedFunc),
     /* 222 */ SyscallDesc("gettid", unimplementedFunc),
     /* 223 */ SyscallDesc("readahead", unimplementedFunc),
@@ -412,9 +414,7 @@ MipsLinuxProcess::MipsLinuxProcess(const std::string &name,
     : MipsLiveProcess(name, objFile, system, stdin_fd, stdout_fd, stderr_fd,
                       argv, envp),
      Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
-{
-    //init_regs->intRegFile[0] = 0;
-}
+{ }
 
 SyscallDesc*
 MipsLinuxProcess::getDesc(int callnum)
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 7831551be..031c2030e 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -1,3 +1,4 @@
+
 /*
  * Copyright (c) 2003-2004 The Regents of The University of Michigan
  * All rights reserved.
@@ -24,74 +25,41 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
+ *          Korey Sewell
  */
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/process.hh"
-#include "arch/mips/linux/process.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
-#include "cpu/exec_context.hh"
-#include "sim/builder.hh"
+#include "cpu/thread_context.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace MipsISA;
 
-
-MipsLiveProcess *
-MipsLiveProcess::create(const std::string &nm, System *system, int stdin_fd,
-        int stdout_fd, int stderr_fd, std::string executable,
-        std::vector<std::string> &argv, std::vector<std::string> &envp)
-{
-    MipsLiveProcess *process = NULL;
-
-    ObjectFile *objFile = createObjectFile(executable);
-    if (objFile == NULL) {
-        fatal("Can't load object file %s", executable);
-    }
-
-
-    if (objFile->getArch() != ObjectFile::Mips)
-        fatal("Object file does not match architecture.");
-    switch (objFile->getOpSys()) {
-      case ObjectFile::Linux:
-        process = new MipsLinuxProcess(nm, objFile, system,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-
-      default:
-        fatal("Unknown/unsupported operating system.");
-    }
-
-    if (process == NULL)
-        fatal("Unknown error creating process object.");
-    return process;
-}
-
 MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile,
         System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
         std::vector<std::string> &argv, std::vector<std::string> &envp)
     : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd,
         argv, envp)
 {
+    // Set up stack. On MIPS, stack starts at the top of kuseg
+    // user address space. MIPS stack grows down from here
+    stack_base = 0x7FFFFFFF;
+
+    // Set pointer for next thread stack.  Reserve 8M for main stack.
+    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
 
-    // XXX all the below need to be updated for SPARC - Ali
+    // Set up break point (Top of Heap)
     brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
     brk_point = roundUp(brk_point, VMPageSize);
 
-    // Set up stack.  On Alpha, stack goes below text section.  This
-    // code should get moved to some architecture-specific spot.
-    stack_base = objFile->textBase() - (409600+4096);
-
-    // Set up region for mmaps.  Tru64 seems to start just above 0 and
-    // grow up from there.
+    // Set up region for mmaps. For now, start at bottom of kuseg space.
     mmap_start = mmap_end = 0x10000;
-
-    // Set pointer for next thread stack.  Reserve 8M for main stack.
-    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
-
 }
 
 void
@@ -99,63 +67,3 @@ MipsLiveProcess::startup()
 {
     argsInit(MachineBytes, VMPageSize);
 }
-
-
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MipsLiveProcess)
-
-    VectorParam<string> cmd;
-    Param<string> executable;
-    Param<string> input;
-    Param<string> output;
-    VectorParam<string> env;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MipsLiveProcess)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MipsLiveProcess)
-
-    INIT_PARAM(cmd, "command line (executable plus arguments)"),
-    INIT_PARAM(executable, "executable (overrides cmd[0] if set)"),
-    INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"),
-    INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"),
-    INIT_PARAM(env, "environment settings"),
-    INIT_PARAM(system, "system")
-
-END_INIT_SIM_OBJECT_PARAMS(MipsLiveProcess)
-
-
-CREATE_SIM_OBJECT(MipsLiveProcess)
-{
-    string in = input;
-    string out = output;
-
-    // initialize file descriptors to default: same as simulator
-    int stdin_fd, stdout_fd, stderr_fd;
-
-    if (in == "stdin" || in == "cin")
-        stdin_fd = STDIN_FILENO;
-    else
-        stdin_fd = Process::openInputFile(input);
-
-    if (out == "stdout" || out == "cout")
-        stdout_fd = STDOUT_FILENO;
-    else if (out == "stderr" || out == "cerr")
-        stdout_fd = STDERR_FILENO;
-    else
-        stdout_fd = Process::openOutputFile(out);
-
-    stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO;
-
-    return MipsLiveProcess::create(getInstanceName(), system,
-                               stdin_fd, stdout_fd, stderr_fd,
-                               (string)executable == "" ? cmd[0] : executable,
-                               cmd, env);
-}
-
-
-REGISTER_SIM_OBJECT("MipsLiveProcess", MipsLiveProcess)
-
-
diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh
index 2a13dc955..b0ef20399 100644
--- a/src/arch/mips/process.hh
+++ b/src/arch/mips/process.hh
@@ -24,6 +24,10 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
+ *          Korey Sewell
  */
 
 #ifndef __MIPS_PROCESS_HH__
@@ -46,18 +50,6 @@ class MipsLiveProcess : public LiveProcess
                 std::vector<std::string> &envp);
 
     void startup();
-
-  public:
-    // this function is used to create the LiveProcess object, since
-    // we can't tell which subclass of LiveProcess to use until we
-    // open and look at the object file.
-    static MipsLiveProcess *create(const std::string &nm,
-                               System *_system,
-                               int stdin_fd, int stdout_fd, int stderr_fd,
-                               std::string executable,
-                               std::vector<std::string> &argv,
-                               std::vector<std::string> &envp);
-
 };
 
 
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 15c6f97f4..61efbb416 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,7 @@
 #include "arch/mips/types.hh"
 #include "arch/mips/constants.hh"
 #include "base/misc.hh"
+#include "base/bitfield.hh"
 #include "config/full_system.hh"
 #include "sim/byteswap.hh"
 #include "sim/faults.hh"
@@ -60,13 +61,17 @@ namespace MipsISA
             switch(width)
             {
               case SingleWidth:
-                void *float_ptr = &regs[floatReg];
-                return *(float *) float_ptr;
+                {
+                    void *float_ptr = &regs[floatReg];
+                    return *(float *) float_ptr;
+                }
 
               case DoubleWidth:
-                uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-                void *double_ptr = &double_val;
-                return *(double *) double_ptr;
+                {
+                    uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+                    void *double_ptr = &double_val;
+                    return *(double *) double_ptr;
+                }
 
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
@@ -95,23 +100,27 @@ namespace MipsISA
             }
         }
 
-        Fault setReg(int floatReg, const FloatReg &val, int width)
+        Fault setReg(int floatReg, const FloatRegVal &val, int width)
         {
-
+            using namespace std;
             switch(width)
             {
               case SingleWidth:
-                float temp = val;
-                void *float_ptr = &temp;
-                regs[floatReg] = *(FloatReg32 *) float_ptr;
-                break;
+                {
+                    float temp = val;
+                    void *float_ptr = &temp;
+                    regs[floatReg] = *(FloatReg32 *) float_ptr;
+                    break;
+                }
 
               case DoubleWidth:
-                const void *double_ptr = &val;
-                FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-                regs[floatReg + 1] = temp_double >> 32;
-                regs[floatReg] = temp_double;
-                break;
+                {
+                    const void *double_ptr = &val;
+                    FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
+                    regs[floatReg + 1] = bits(temp_double, 63, 32);
+                    regs[floatReg] = bits(temp_double, 31, 0);
+                    break;
+                }
 
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
@@ -131,8 +140,8 @@ namespace MipsISA
                 break;
 
               case DoubleWidth:
-                regs[floatReg + 1] = val >> 32;
-                regs[floatReg] = val;
+                regs[floatReg + 1] = bits(val, 63, 32);
+                regs[floatReg] = bits(val, 31, 0);
                 break;
 
               default:
@@ -146,14 +155,6 @@ namespace MipsISA
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    enum MiscFloatRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 3cd87734d..5add1b7be 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_INT_REGFILE_HH__
@@ -35,7 +37,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 class Regfile;
 
 namespace MipsISA
@@ -63,11 +65,6 @@ namespace MipsISA
 
     };
 
-    enum MiscIntRegNums {
-       HI = NumIntArchRegs,
-       LO
-    };
-
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 9f054e5f7..87961f97e 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_MISC_REGFILE_HH__
@@ -34,7 +36,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 class Regfile;
 
 namespace MipsISA
@@ -43,26 +45,20 @@ namespace MipsISA
 
       protected:
         uint64_t	fpcr;		// floating point condition codes
-        uint64_t	uniq;		// process-unique register
         bool		lock_flag;	// lock flag for LL/SC
         Addr		lock_addr;	// lock address for LL/SC
 
         MiscReg miscRegFile[NumMiscRegs];
 
       public:
-        //These functions should be removed once the simplescalar cpu model
-        //has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
-        void copyMiscRegs(ExecContext *xc);
+        void copyMiscRegs(ThreadContext *tc);
 
         MiscReg readReg(int misc_reg)
         {
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
+        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
@@ -73,22 +69,11 @@ namespace MipsISA
         }
 
         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                               ExecContext *xc)
+                               ThreadContext *tc)
         {
             miscRegFile[misc_reg] = val; return NoFault;
         }
 
-#if FULL_SYSTEM
-        void clearIprs() { }
-
-      protected:
-        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-      private:
-        MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
-
-        Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
-#endif
         friend class RegFile;
     };
 } // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index e77571b33..a68120299 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_REGFILE_HH__
@@ -37,7 +39,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 
 namespace MipsISA
 {
@@ -62,10 +64,10 @@ namespace MipsISA
         }
 
         MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ExecContext *xc)
+                Fault &fault, ThreadContext *tc)
         {
             fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
         }
 
         Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -74,17 +76,17 @@ namespace MipsISA
         }
 
         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc)
+                ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+            return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
-        FloatReg readFloatReg(int floatReg)
+        FloatRegVal readFloatReg(int floatReg)
         {
             return floatRegFile.readReg(floatReg,SingleWidth);
         }
 
-        FloatReg readFloatReg(int floatReg, int width)
+        FloatRegVal readFloatReg(int floatReg, int width)
         {
             return floatRegFile.readReg(floatReg,width);
         }
@@ -99,12 +101,12 @@ namespace MipsISA
             return floatRegFile.readRegBits(floatReg,width);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val)
+        Fault setFloatReg(int floatReg, const FloatRegVal &val)
         {
             return floatRegFile.setReg(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
         {
             return floatRegFile.setReg(floatReg, val, width);
         }
@@ -166,16 +168,6 @@ namespace MipsISA
             nnpc = val;
         }
 
-
-#if FULL_SYSTEM
-        IntReg palregs[NumIntRegs];	// PAL shadow registers
-        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
-        int intrflag;			// interrupt flag
-        bool pal_shadow;		// using pal_shadow registers
-        inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
-        inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
-#endif // FULL_SYSTEM
-
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
 
@@ -187,13 +179,10 @@ namespace MipsISA
         }
     };
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
-#if FULL_SYSTEM
-    void copyIprs(ExecContext *src, ExecContext *dest);
-#endif
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index 1d8d97a79..f9e092dbd 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -24,21 +24,23 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
-#ifndef __ARCH_ALPHA_STACKTRACE_HH__
-#define __ARCH_ALPHA_STACKTRACE_HH__
+#ifndef __ARCH_MIPS_STACKTRACE_HH__
+#define __ARCH_MIPS_STACKTRACE_HH__
 
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
-class ExecContext;
+class ThreadContext;
 class StackTrace;
 
 class ProcessInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
     int thread_info_size;
     int task_struct_size;
@@ -47,7 +49,7 @@ class ProcessInfo
     int name_off;
 
   public:
-    ProcessInfo(ExecContext *_xc);
+    ProcessInfo(ThreadContext *_tc);
 
     Addr task(Addr ksp) const;
     int pid(Addr ksp) const;
@@ -59,7 +61,7 @@ class StackTrace
   protected:
     typedef TheISA::MachInst MachInst;
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
     std::vector<Addr> stack;
 
   private:
@@ -68,21 +70,21 @@ class StackTrace
     bool decodeSave(MachInst inst, int &reg, int &disp);
     bool decodeStack(MachInst inst, int &disp);
 
-    void trace(ExecContext *xc, bool is_call);
+    void trace(ThreadContext *tc, bool is_call);
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
+    StackTrace(ThreadContext *tc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
     {
-        xc = 0;
+        tc = 0;
         stack.clear();
     }
 
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
+    bool valid() const { return tc != NULL; }
+    bool trace(ThreadContext *tc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -104,7 +106,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
@@ -112,8 +114,8 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
     if (valid())
         clear();
 
-    trace(xc, !inst->isReturn());
+    trace(tc, !inst->isReturn());
     return true;
 }
 
-#endif // __ARCH_ALPHA_STACKTRACE_HH__
+#endif // __ARCH_MIPS_STACKTRACE_HH__
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 4d5fb3456..6330044d9 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_TYPES_HH__
@@ -40,14 +42,15 @@ namespace MipsISA
     typedef uint32_t IntReg;
 
     // floating point register file entry type
-    typedef double FloatReg;
     typedef uint32_t FloatReg32;
     typedef uint64_t FloatReg64;
     typedef uint64_t FloatRegBits;
 
+    typedef double FloatRegVal;
+    typedef double FloatReg;
+
     // cop-0/cop-1 system control register
     typedef uint64_t MiscReg;
-    typedef uint64_t InternalProcReg;
 
     typedef union {
         IntReg   intreg;
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
new file mode 100644
index 000000000..e7455fdbf
--- /dev/null
+++ b/src/arch/mips/utility.cc
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
+#include "config/full_system.hh"
+#include "cpu/static_inst.hh"
+#include "sim/serialize.hh"
+#include "base/bitfield.hh"
+
+using namespace MipsISA;
+using namespace std;
+
+uint64_t
+MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
+{
+
+    switch (cvt_type)
+    {
+      case SINGLE_TO_DOUBLE:
+        {
+            double sdouble_val = fp_val;
+            void  *sdouble_ptr = &sdouble_val;
+            uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
+            return sdp_bits;
+        }
+
+      case SINGLE_TO_WORD:
+        {
+            int32_t sword_val  = (int32_t) fp_val;
+            void  *sword_ptr   = &sword_val;
+            uint64_t sword_bits= *(uint32_t *) sword_ptr;
+            return sword_bits;
+        }
+
+      case WORD_TO_SINGLE:
+        {
+            float wfloat_val   = fp_val;
+            void  *wfloat_ptr  = &wfloat_val;
+            uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
+            return wfloat_bits;
+        }
+
+      case WORD_TO_DOUBLE:
+        {
+            double wdouble_val = fp_val;
+            void  *wdouble_ptr = &wdouble_val;
+            uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
+            return wdp_bits;
+        }
+
+      default:
+        panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
+        return 0;
+    }
+}
+
+double
+MipsISA::roundFP(double val, int digits)
+{
+    double digit_offset = pow(10.0,digits);
+    val = val * digit_offset;
+    val = val + 0.5;
+    val = floor(val);
+    val = val / digit_offset;
+    return val;
+}
+
+double
+MipsISA::truncFP(double val)
+{
+    int trunc_val = (int) val;
+    return (double) trunc_val;
+}
+
+bool
+MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
+{
+    int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
+    bool cc_val = (fcsr >> shift) & 0x00000001;
+    return cc_val;
+}
+
+uint32_t
+MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
+{
+    int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
+
+    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+           cc_val << cc_idx |
+           bits(fcsr, cc_idx - 1, 0);
+
+    return fcsr;
+}
+
+uint32_t
+MipsISA::genInvalidVector(uint32_t fcsr_bits)
+{
+    //Set FCSR invalid in "flag" field
+    int invalid_offset = Invalid + Flag_Field;
+    fcsr_bits = fcsr_bits | (1 << invalid_offset);
+
+    //Set FCSR invalid in "cause" flag
+    int cause_offset = Invalid + Cause_Field;
+    fcsr_bits = fcsr_bits | (1 << cause_offset);
+
+    return fcsr_bits;
+}
+
+bool
+MipsISA::isNan(void *val_ptr, int size)
+{
+    switch (size)
+    {
+      case 32:
+        {
+            uint32_t val_bits = *(uint32_t *) val_ptr;
+            return (bits(val_bits, 30, 23) == 0xFF);
+        }
+
+      case 64:
+        {
+            uint64_t val_bits = *(uint64_t *) val_ptr;
+            return (bits(val_bits, 62, 52) == 0x7FF);
+        }
+
+      default:
+        panic("Type unsupported. Size mismatch\n");
+    }
+}
+
+
+bool
+MipsISA::isQnan(void *val_ptr, int size)
+{
+    switch (size)
+    {
+      case 32:
+        {
+            uint32_t val_bits = *(uint32_t *) val_ptr;
+            return (bits(val_bits, 30, 22) == 0x1FE);
+        }
+
+      case 64:
+        {
+            uint64_t val_bits = *(uint64_t *) val_ptr;
+            return (bits(val_bits, 62, 51) == 0xFFE);
+        }
+
+      default:
+        panic("Type unsupported. Size mismatch\n");
+    }
+}
+
+bool
+MipsISA::isSnan(void *val_ptr, int size)
+{
+    switch (size)
+    {
+      case 32:
+        {
+            uint32_t val_bits = *(uint32_t *) val_ptr;
+            return (bits(val_bits, 30, 22) == 0x1FF);
+        }
+
+      case 64:
+        {
+            uint64_t val_bits = *(uint64_t *) val_ptr;
+            return (bits(val_bits, 62, 51) == 0xFFF);
+        }
+
+      default:
+        panic("Type unsupported. Size mismatch\n");
+    }
+}
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 5c7dc3ea4..c5c69ddcd 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -39,6 +39,19 @@
 
 namespace MipsISA {
 
+    //Floating Point Utility Functions
+    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
+    double roundFP(double val, int digits);
+    double truncFP(double val);
+
+    bool getCondCode(uint32_t fcsr, int cc);
+    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
+    uint32_t genInvalidVector(uint32_t fcsr);
+
+    bool isNan(void *val_ptr, int size);
+    bool isQnan(void *val_ptr, int size);
+    bool isSnan(void *val_ptr, int size);
 };
 
+
 #endif
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 7362c9275..e7a8278db 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -25,6 +25,9 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+#          Steve Reinhardt
 
 import os
 import sys
@@ -47,12 +50,8 @@ base_sources = Split('''
 
 # Full-system sources
 full_system_sources = Split('''
-	tlb.cc
-	arguments.cc
-	ev5.cc
-	osfpal.cc
-	stacktrace.cc
 	vtophys.cc
+	ua2005.cc
 	''')
 
 # Syscall emulation (non-full-system) sources
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 67a89ab0e..7b7765935 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -24,12 +24,19 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Kevin Lim
  */
 
 #include "arch/sparc/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
+#if !FULL_SYSTEM
+#include "sim/process.hh"
+#include "mem/page_table.hh"
+#endif
 
 namespace SparcISA
 {
@@ -215,40 +222,66 @@ TrapType      TrapInstruction::_baseTrapType = 0x100;
 FaultPriority TrapInstruction::_priority = 16;
 FaultStat     TrapInstruction::_count;
 
+#if !FULL_SYSTEM
+FaultName PageTableFault::_name = "page_table_fault";
+TrapType PageTableFault::_trapType = 0x0000;
+FaultPriority PageTableFault::_priority = 0;
+FaultStat PageTableFault::_count;
+#endif
+
 #if FULL_SYSTEM
 
-void SparcFault::invoke(ExecContext * xc)
+void SparcFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     countStat()++;
 
     //Use the SPARC trap state machine
     /*// exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
+    if (setRestartAddress() || !tc->inPalMode())
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
-    if (!xc->inPalMode())
-        AlphaISA::swap_palshadow(&(xc->regs), true);
+    if (!tc->inPalMode())
+        AlphaISA::swap_palshadow(&(tc->regs), true);
 
-    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
-    xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
+    tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
+    tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
 }
 
 #endif
 
 #if !FULL_SYSTEM
 
-void TrapInstruction::invoke(ExecContext * xc)
+void TrapInstruction::invoke(ThreadContext * tc)
 {
-    xc->syscall(syscall_num);
+    // Should be handled in ISA.
 }
 
+void PageTableFault::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+
+    // address is higher than the stack region or in the current stack region
+    if (vaddr > p->stack_base || vaddr > p->stack_min)
+        FaultBase::invoke(tc);
+
+    // We've accessed the next page
+    if (vaddr > p->stack_min - PageBytes) {
+        p->stack_min -= PageBytes;
+        if (p->stack_base - p->stack_min > 8*1024*1024)
+            fatal("Over max stack size for one thread\n");
+        p->pTable->allocate(p->stack_min, PageBytes);
+        warn("Increasing stack size by one page.");
+    } else {
+        FaultBase::invoke(tc);
+    }
+}
 #endif
 
 } // namespace SparcISA
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index e8fb8dfc5..b279f4911 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Kevin Lim
  */
 
 #ifndef __ALPHA_FAULTS_HH__
@@ -43,7 +46,7 @@ class SparcFault : public FaultBase
 {
   public:
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
     virtual TrapType trapType() = 0;
     virtual FaultPriority priority() = 0;
@@ -80,6 +83,31 @@ class MemAddressNotAligned : public SparcFault
     bool isAlignmentFault() {return true;}
 };
 
+#if !FULL_SYSTEM
+class PageTableFault : public SparcFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static TrapType _trapType;
+    static FaultPriority _priority;
+    static FaultStat _count;
+  public:
+    PageTableFault(Addr va)
+        : vaddr(va) {}
+    FaultName name() {return _name;}
+    TrapType trapType() {return _trapType;}
+    FaultPriority priority() {return _priority;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+static inline Fault genPageTableFault(Addr va)
+{
+    return new PageTableFault(va);
+}
+#endif
+
 static inline Fault genMachineCheckFault()
 {
     return new InternalProcessorError;
@@ -582,10 +610,11 @@ class TrapInstruction : public EnumeratedFault
     FaultPriority priority() {return _priority;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
+
 } // SparcISA namespace
 
 #endif // __FAULTS_HH__
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index c6e05bf6f..fa8832920 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -44,13 +44,13 @@ decode OP default Unknown::unknown()
             format Branch19
             {
                 0x0: bpcci({{
-                    if(passesCondition(CcrIcc, COND2))
+                    if(passesCondition(Ccr<3:0>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
                 }});
                 0x2: bpccx({{
-                    if(passesCondition(CcrXcc, COND2))
+                    if(passesCondition(Ccr<7:4>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
@@ -58,7 +58,7 @@ decode OP default Unknown::unknown()
             }
         }
         0x2: Branch22::bicc({{
-            if(passesCondition(CcrIcc, COND2))
+            if(passesCondition(Ccr<3:0>, COND2))
                 NNPC = xc->readPC() + disp;
             else
                 handle_annul
@@ -124,17 +124,17 @@ decode OP default Unknown::unknown()
             0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
             0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
             0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
-            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
+            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
             0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
             0x0A: umul({{
                 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
-                YValue = Rd<63:32>;
+                Y = Rd<63:32>;
             }});
             0x0B: smul({{
                 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
-                YValue = Rd.sdw;
+                Y = Rd.sdw;
             }});
-            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
+            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}});
             0x0D: udivx({{
                 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
                 else Rd.udw = Rs1.udw / Rs2_or_imm13;
@@ -143,7 +143,7 @@ decode OP default Unknown::unknown()
                 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
                 else
                 {
-                    Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
+                    Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
                     if(Rd.udw >> 32 != 0)
                         Rd.udw = 0xFFFFFFFF;
                 }
@@ -153,7 +153,7 @@ decode OP default Unknown::unknown()
                     fault = new DivisionByZero;
                 else
                 {
-                    Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
+                    Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
                     if(Rd.udw<63:31> != 0)
                         Rd.udw = 0x7FFFFFFF;
                     else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
@@ -187,7 +187,7 @@ decode OP default Unknown::unknown()
             0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
             0x18: addccc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
-                int64_t carryin = CcrIccC;
+                int64_t carryin = Ccr<0:0>;
                 Rd = resTemp = Rs1 + val2 + carryin;}},
                 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
@@ -198,16 +198,16 @@ decode OP default Unknown::unknown()
             0x1A: umulcc({{
                 uint64_t resTemp;
                 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
-                YValue = resTemp<63:32>;}},
+                Y = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1B: smulcc({{
                 int64_t resTemp;
                 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
-                YValue = resTemp<63:32>;}},
+                Y = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1C: subccc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
-                int64_t carryin = CcrIccC;
+                int64_t carryin = Ccr<0:0>;
                 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
                 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
                 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
@@ -224,7 +224,7 @@ decode OP default Unknown::unknown()
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
-                    resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
+                    resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
                     overflow = (resTemp<63:32> != 0);
                     if(overflow) Rd = resTemp = 0xFFFFFFFF;
                     else Rd = resTemp;
@@ -240,7 +240,7 @@ decode OP default Unknown::unknown()
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
-                    Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
+                    Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
                     overflow = (resTemp<63:31> != 0);
                     underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
                     if(overflow) Rd = resTemp = 0x7FFFFFFF;
@@ -295,12 +295,12 @@ decode OP default Unknown::unknown()
                 int32_t multiplier = Rs1<31:0>;
                 int32_t savedLSB = Rs1<0:>;
                 multiplier = multiplier<31:1> |
-                    ((CcrIccN
-                    ^ CcrIccV) << 32);
-                if(!YValue<0:>)
+                    ((Ccr<3:3>
+                    ^ Ccr<1:1>) << 32);
+                if(!Y<0:>)
                     multiplicand = 0;
                 Rd = resTemp = multiplicand + multiplier;
-                YValue = YValue<31:1> | (savedLSB << 31);}},
+                Y = Y<31:1> | (savedLSB << 31);}},
                 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
                 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
                 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
@@ -321,56 +321,27 @@ decode OP default Unknown::unknown()
                 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
                 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
             }
-            0x28: decode RS1 {
-                0x0: rdy({{Rd = YValue;}});
-                0x2: rdccr({{Rd = Ccr;}});
-                0x3: rdasi({{Rd = Asi;}});
-                0x4: PrivTick::rdtick({{Rd = Tick;}});
-                0x5: rdpc({{Rd = xc->readPC();}});
-                0x6: rdfprs({{Rd = Fprs;}});
-                0xF: decode I {
-                    0x0: Nop::membar({{/*Membar isn't needed yet*/}});
-                    0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
-                }
-            }
-            0x2A: decode RS1 {
-                format Priv
-                {
-                    0x0: rdprtpc({{
-                        Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
-                    }});
-                    0x1: rdprtnpc({{
-                        Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
-                    }});
-                    0x2: rdprtstate({{
-                        Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
-                    }});
-                    0x3: rdprtt({{
-                        Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
-                    }});
-                    0x4: rdprtick({{Rd = Tick;}});
-                    0x5: rdprtba({{Rd = Tba;}});
-                    0x6: rdprpstate({{Rd = Pstate;}});
-                    0x7: rdprtl({{Rd = Tl;}});
-                    0x8: rdprpil({{Rd = Pil;}});
-                    0x9: rdprcwp({{Rd = Cwp;}});
-                    0xA: rdprcansave({{Rd = Cansave;}});
-                    0xB: rdprcanrestore({{Rd = Canrestore;}});
-                    0xC: rdprcleanwin({{Rd = Cleanwin;}});
-                    0xD: rdprotherwin({{Rd = Otherwin;}});
-                    0xE: rdprwstate({{Rd = Wstate;}});
-                }
-                //The floating point queue isn't implemented right now.
-                0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
-                0x1F: Priv::rdprver({{Rd = Ver;}});
-            }
+            // XXX might want a format rdipr thing here
+            0x28: rdasr({{
+                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
+            }});
+            0x29: rdhpr({{
+                // XXX Need to protect with format that traps non-priv/priv
+                // access
+                Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
+            }});
+            0x2A: rdpr({{
+                // XXX Need to protect with format that traps non-priv
+                // access
+                Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
+            }});
             0x2B: BasicOperate::flushw({{
                 if(NWindows - 2 - Cansave == 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(WstateOther);
+                        fault = new SpillNOther(Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(WstateNormal);
+                        fault = new SpillNNormal(Wstate<2:0>);
                 }
             }});
             0x2C: decode MOVCC3
@@ -379,13 +350,13 @@ decode OP default Unknown::unknown()
                 0x1: decode CC
                 {
                     0x0: movcci({{
-                        if(passesCondition(CcrIcc, COND4))
+                        if(passesCondition(Ccr<3:0>, COND4))
                             Rd = Rs2_or_imm11;
                         else
                             Rd = Rd;
                     }});
                     0x2: movccx({{
-                        if(passesCondition(CcrXcc, COND4))
+                        if(passesCondition(Ccr<7:4>, COND4))
                             Rd = Rs2_or_imm11;
                         else
                             Rd = Rd;
@@ -419,49 +390,23 @@ decode OP default Unknown::unknown()
                 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
                 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
             }
-            0x30: decode RD {
-                0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
-                0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
-                0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
-                0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
-                0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
-            }
+            0x30: wrasr({{
+                xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
+            }});
             0x31: decode FCN {
                 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
                 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
             }
-            0x32: decode RD {
-                format Priv
-                {
-                    0x0: wrprtpc({{
-                        xc->setMiscReg(MISCREG_TPC_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x1: wrprtnpc({{
-                        xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x2: wrprtstate({{
-                        xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x3: wrprtt({{
-                        xc->setMiscReg(MISCREG_TT_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
-                    0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
-                    0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
-                    0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
-                    0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
-                    0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
-                    0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
-                    0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
-                    0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
-                    0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
-                    0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
-                }
-            }
+            0x32: wrpr({{
+                // XXX Need to protect with format that traps non-priv
+                // access
+                xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+            }});
+            0x33: wrhpr({{
+                // XXX Need to protect with format that traps non-priv/priv
+                // access
+                xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+            }});
             0x34: Trap::fpop1({{fault = new FpDisabled;}});
             0x35: Trap::fpop2({{fault = new FpDisabled;}});
             0x38: Branch::jmpl({{
@@ -492,9 +437,9 @@ decode OP default Unknown::unknown()
                     if(Canrestore == 0)
                     {
                         if(Otherwin)
-                            fault = new FillNOther(WstateOther);
+                            fault = new FillNOther(Wstate<5:3>);
                         else
-                            fault = new FillNNormal(WstateNormal);
+                            fault = new FillNNormal(Wstate<2:0>);
                     }
                     else
                     {
@@ -511,7 +456,7 @@ decode OP default Unknown::unknown()
             0x3A: decode CC
             {
                 0x0: Trap::tcci({{
-                    if(passesCondition(CcrIcc, COND2))
+                    if(passesCondition(Ccr<3:0>, COND2))
                     {
                         int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
@@ -524,7 +469,7 @@ decode OP default Unknown::unknown()
                     }
                 }});
                 0x2: Trap::tccx({{
-                    if(passesCondition(CcrXcc, COND2))
+                    if(passesCondition(Ccr<7:4>, COND2))
                     {
                         int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
@@ -545,9 +490,9 @@ decode OP default Unknown::unknown()
                 if(Cansave == 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(WstateOther);
+                        fault = new SpillNOther(Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(WstateNormal);
+                        fault = new SpillNNormal(Wstate<2:0>);
                     Cwp = (Cwp + 2) % NWindows;
                 }
                 else if(Cleanwin - Canrestore == 0)
@@ -575,9 +520,9 @@ decode OP default Unknown::unknown()
                 if(Canrestore == 0)
                 {
                     if(Otherwin)
-                        fault = new FillNOther(WstateOther);
+                        fault = new FillNOther(Wstate<5:3>);
                     else
-                        fault = new FillNNormal(WstateNormal);
+                        fault = new FillNNormal(Wstate<2:0>);
                 }
                 else
                 {
@@ -594,23 +539,26 @@ decode OP default Unknown::unknown()
                 0x0: Priv::done({{
                     if(Tl == 0)
                         return new IllegalInstruction;
-                    Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
-                    Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
-                    Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
-                    Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
-                    NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
-                    NNPC = NPC + 4;
+
+                    Cwp = Tstate<4:0>;
+                    Pstate = Tstate<20:8>;
+                    Asi = Tstate<31:24>;
+                    Ccr = Tstate<39:32>;
+                    Gl = Tstate<42:40>;
+                    NPC = Tnpc;
+                    NNPC = Tnpc + 4;
                     Tl = Tl - 1;
                 }});
                 0x1: BasicOperate::retry({{
                     if(Tl == 0)
                         return new IllegalInstruction;
-                    Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
-                    Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
-                    Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
-                    Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
-                    NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
-                    NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
+                    Cwp = Tstate<4:0>;
+                    Pstate = Tstate<20:8>;
+                    Asi = Tstate<31:24>;
+                    Ccr = Tstate<39:32>;
+                    Gl = Tstate<42:40>;
+                    NPC = Tpc;
+                    NNPC = Tnpc + 4;
                     Tl = Tl - 1;
                 }});
             }
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 1fd87b1d3..1894ce541 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -316,22 +316,38 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 
     calcCcCode = '''
-        CcrIccN = (Rd >> 31) & 1;
-        CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
-        CcrXccN = (Rd >> 63) & 1;
-        CcrXccZ = (Rd == 0);
-        CcrIccV = %(ivValue)s;
-        CcrIccC = %(icValue)s;
-        CcrXccV = %(xvValue)s;
-        CcrXccC = %(xcValue)s;
-        DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
-        DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
-        DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
-        DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
-        DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
-        DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
-        DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
-        DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
+        uint8_t tmp_ccriccc;
+        uint8_t tmp_ccriccv;
+        uint8_t tmp_ccriccz;
+        uint8_t tmp_ccriccn;
+        uint8_t tmp_ccrxccc;
+        uint8_t tmp_ccrxccv;
+        uint8_t tmp_ccrxccz;
+        uint8_t tmp_ccrxccn;
+
+        tmp_ccriccn = (Rd >> 31) & 1;
+        tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0);
+        tmp_ccrxccn = (Rd >> 63) & 1;
+        tmp_ccrxccz = (Rd == 0);
+        tmp_ccriccv = %(ivValue)s & 1;
+        tmp_ccriccc = %(icValue)s & 1;
+        tmp_ccrxccv = %(xvValue)s & 1;
+        tmp_ccrxccc = %(xcValue)s & 1;
+
+        Ccr =  tmp_ccriccc | tmp_ccriccv << 1 |
+               tmp_ccriccz << 2 | tmp_ccriccn << 3|
+               tmp_ccrxccc << 4 | tmp_ccrxccv << 5|
+               tmp_ccrxccz << 6| tmp_ccrxccn << 7;
+
+
+        DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn);
+        DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz);
+        DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn);
+        DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz);
+        DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv);
+        DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc);
+        DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv);
+        DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc);
         '''
 }};
 
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index a8de22c0e..7df59d736 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -51,23 +51,6 @@ output header {{
         };
 
         /**
-         * Base class for user mode "tick" access.
-         */
-        class PrivTick : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            PrivTick(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
          * Base class for privelege mode operations with immediates.
          */
         class PrivImm : public Priv
@@ -83,21 +66,6 @@ output header {{
             int32_t imm;
         };
 
-        /**
-         * Base class for user mode "tick" access with immediates.
-         */
-        class PrivTickImm : public PrivTick
-        {
-          protected:
-            // Constructor
-            PrivTickImm(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
-            {
-            }
-
-            int32_t imm;
-        };
 }};
 
 output decoder {{
@@ -106,12 +74,6 @@ output decoder {{
         {
                 return "Privileged Instruction";
         }
-
-        std::string PrivTick::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-                return "Regular access to Tick";
-        }
 }};
 
 def template PrivExecute {{
@@ -154,16 +116,10 @@ let {{
 
 // Primary format for integer operate instructions:
 def format Priv(code, *opt_flags) {{
-        checkCode = "(!PstatePriv)"
+        checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)"
         (header_output, decoder_output,
          exec_output, decode_block) = doPrivFormat(code,
              checkCode, name, Name, opt_flags)
 }};
 
-// Primary format for integer operate instructions:
-def format PrivTick(code, *opt_flags) {{
-        checkCode = "(!PstatePriv && TickNpt)"
-        (header_output, decoder_output,
-         exec_output, decode_block) = doPrivFormat(code,
-             checkCode, name, Name, opt_flags)
-}};
+
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 762de243a..40afb3722 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -48,7 +48,7 @@ output header {{
 output decoder {{
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+#include "cpu/thread_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
 #if defined(linux)
diff --git a/src/arch/sparc/isa/main.isa b/src/arch/sparc/isa/main.isa
index 35167d6b7..14acf54fa 100644
--- a/src/arch/sparc/isa/main.isa
+++ b/src/arch/sparc/isa/main.isa
@@ -25,7 +25,16 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// SPARC ISA description file.
+//
+////////////////////////////////////////////////////////////////////
 
+//Include the C++ include directives
 ##include "includes.isa"
 
 ////////////////////////////////////////////////////////////////////
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index a89034e30..9e5c783e8 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -63,83 +63,26 @@ def operands {{
     'R1':  		('IntReg', 'udw', '1', None, 7),
     'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
     'R16': 		('IntReg', 'udw', '16', None, 9),
+
     # Control registers
-    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
-    'PstateAg':		('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
-    'PstateIe':		('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
-    'PstatePriv':	('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
-    'PstateAm':		('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
-    'PstatePef':	('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
-    'PstateRed':	('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
-    'PstateMm':		('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
-    'PstateTle':	('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
-    'PstateCle':	('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
-    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
     'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 12),
-    'YValue':		('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
-    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
-    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
-    #'Tt':		('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
     'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
-    'CcrIcc':		('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
-    'CcrIccC':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
-    'CcrIccV':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
-    'CcrIccZ':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
-    'CcrIccN':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
-    'CcrXcc':		('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
-    'CcrXccC':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
-    'CcrXccV':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
-    'CcrXccZ':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
-    'CcrXccN':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
     'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
+
+    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
+    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 28),
+    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28),
+    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
     'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 27),
-    #'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
-    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
-    'TickCounter':	('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
-    'TickNpt':		('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
+
+    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
     'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
     'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
-    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
     'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
+    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
     'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
-    'WstateNormal':	('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
-    'WstateOther':	('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
-    'Ver':		('ControlReg', 'udw', 'MISCREG_VER', None, 41),
-    'VerMaxwin':	('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
-    'VerMaxtl':		('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
-    'VerMask':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
-    'VerImpl':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
-    'VerManuf':		('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
-    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
-    'FsrCexc':		('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
-    'FsrCexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
-    'FsrCexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
-    'FsrCexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
-    'FsrCexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
-    'FsrCexcNvc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
-    'FsrAexc':		('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
-    'FsrAexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
-    'FsrAexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
-    'FsrAexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
-    'FsrAexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
-    'FsrAexcNvc':	('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
-    'FsrFcc0':		('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
-    'FsrQne':		('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
-    'FsrFtt':		('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
-    'FsrVer':		('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
-    'FsrNs':		('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
-    'FsrTem':		('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
-    'FsrTemNxm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
-    'FsrTemDzm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
-    'FsrTemUfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
-    'FsrTemOfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
-    'FsrTemNvm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
-    'FsrRd':		('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
-    'FsrFcc1':		('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
-    'FsrFcc2':		('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
-    'FsrFcc3':		('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
-    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
-    'FprsDl':		('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
-    'FprsDu':		('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
-    'FprsFef':		('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
+    'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 12),
+
+    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47)
+
 }};
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 453d14664..346f7b730 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ *          Gabe Black
  */
 
 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
@@ -33,7 +36,7 @@
 #include "config/full_system.hh"
 #include "sim/host.hh"
 
-class ExecContext;
+class ThreadContext;
 class FastCPU;
 //class FullCPU;
 class Checkpoint;
@@ -80,6 +83,9 @@ class SyscallReturn
 
 #endif
 
+#if FULL_SYSTEM
+#include "arch/sparc/isa_fullsys_traits.hh"
+#endif
 
 namespace SparcISA
 {
@@ -172,12 +178,12 @@ namespace SparcISA
         // indicate success/failure in reg the carry bit of the ccr
         // and put the return value itself in the standard return value reg ().
         if (return_value.successful()) {
-            // no error
-            regs->setMiscReg(MISCREG_CCR_XCC_C, 0);
+            // no error, clear XCC.C
+            regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF);
             regs->setIntReg(ReturnValueReg, return_value.value());
         } else {
-            // got an error, return details
-            regs->setMiscReg(MISCREG_CCR_XCC_C, 1);
+            // got an error, set XCC.C
+            regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10);
             regs->setIntReg(ReturnValueReg, return_value.value());
         }
     }
diff --git a/src/arch/sparc/linux/linux.cc b/src/arch/sparc/linux/linux.cc
index c7ed29358..ae6ffbc2a 100644
--- a/src/arch/sparc/linux/linux.cc
+++ b/src/arch/sparc/linux/linux.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
  */
 
 #include "arch/sparc/linux/linux.hh"
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index 9cde5bb9c..926c2cb77 100644
--- a/src/arch/sparc/linux/linux.hh
+++ b/src/arch/sparc/linux/linux.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
  */
 
 #ifndef __ARCH_SPARC_LINUX_LINUX_HH__
diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc
index 71be6a83a..e27255e67 100644
--- a/src/arch/sparc/linux/process.cc
+++ b/src/arch/sparc/linux/process.cc
@@ -24,6 +24,10 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Gabe Black
+ *          Ali Saidi
  */
 
 #include "arch/sparc/isa_traits.hh"
@@ -31,7 +35,7 @@
 #include "arch/sparc/regfile.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"
 
 #include "sim/process.hh"
@@ -44,9 +48,9 @@ using namespace SparcISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -54,40 +58,40 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "sparc");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
 
     return 0;
 }
 
 
 SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num,
-                                         Process *p, ExecContext *xc)
+                                         Process *p, ThreadContext *tc)
 {
     const IntReg id = htog(100);
-    Addr ruid = xc->getSyscallArg(0);
-    Addr euid = xc->getSyscallArg(1);
-    Addr suid = xc->getSyscallArg(2);
+    Addr ruid = tc->getSyscallArg(0);
+    Addr euid = tc->getSyscallArg(1);
+    Addr suid = tc->getSyscallArg(2);
     //Handle the EFAULT case
     //Set the ruid
     if(ruid)
     {
         BufferArg ruidBuff(ruid, sizeof(IntReg));
         memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
-        ruidBuff.copyOut(xc->getMemPort());
+        ruidBuff.copyOut(tc->getMemPort());
     }
     //Set the euid
     if(euid)
     {
         BufferArg euidBuff(euid, sizeof(IntReg));
         memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
-        euidBuff.copyOut(xc->getMemPort());
+        euidBuff.copyOut(tc->getMemPort());
     }
     //Set the suid
     if(suid)
     {
         BufferArg suidBuff(suid, sizeof(IntReg));
         memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
-        suidBuff.copyOut(xc->getMemPort());
+        suidBuff.copyOut(tc->getMemPort());
     }
     return 0;
 }
diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh
index 23ce66d02..f4819ba84 100644
--- a/src/arch/sparc/linux/process.hh
+++ b/src/arch/sparc/linux/process.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
  */
 
 #ifndef __SPARC_LINUX_PROCESS_HH__
@@ -59,7 +61,7 @@ class SparcLinuxProcess : public SparcLiveProcess
 };
 
 SyscallReturn getresuidFunc(SyscallDesc *desc, int num,
-                                 Process *p, ExecContext *xc);
+                                 Process *p, ThreadContext *tc);
 
 } // namespace SparcISA
 #endif // __ALPHA_LINUX_PROCESS_HH__
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 250c1bec4..75f01e038 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -24,60 +24,23 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/process.hh"
-#include "arch/sparc/linux/process.hh"
-#include "arch/sparc/solaris/process.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/translating_port.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace SparcISA;
 
-SparcLiveProcess *
-SparcLiveProcess::create(const std::string &nm, System *system, int stdin_fd,
-        int stdout_fd, int stderr_fd, std::string executable,
-        std::vector<std::string> &argv, std::vector<std::string> &envp)
-{
-    SparcLiveProcess *process = NULL;
-
-    ObjectFile *objFile = createObjectFile(executable);
-    if (objFile == NULL) {
-        fatal("Can't load object file %s", executable);
-    }
-
-
-    if (objFile->getArch() != ObjectFile::SPARC)
-        fatal("Object file with arch %x does not match architecture %x.",
-                objFile->getArch(), ObjectFile::SPARC);
-    switch (objFile->getOpSys()) {
-      case ObjectFile::Linux:
-        process = new SparcLinuxProcess(nm, objFile, system,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-
-
-      case ObjectFile::Solaris:
-        process = new SparcSolarisProcess(nm, objFile, system,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-      default:
-        fatal("Unknown/unsupported operating system.");
-    }
-
-    if (process == NULL)
-        fatal("Unknown error creating process object.");
-    return process;
-}
 
 SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
         System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
@@ -110,36 +73,27 @@ SparcLiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_PRIV, 0);
-    //Interrupts are enabled
-    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_IE, 1);
-    //Round to nearest
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_RD, 0);
-    //Floating point traps are not enabled
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_TEM, 0);
-    //Turn non standard mode off
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_NS, 0);
-    //The floating point queue is empty
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_QNE, 0);
-    //There are no accrued eexecContext[0]eptions
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_AEXC, 0);
-    //There are no current eexecContext[0]eptions
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_CEXC, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+
+    //Setup default FP state
+    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
 
+    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
     //There are no windows to pop
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
     //All windows are available to save into
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
     //All windows are "clean"
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
     //Start with register window 0
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
 }
 
 m5_auxv_t buildAuxVect(int64_t type, int64_t val)
@@ -317,72 +271,14 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
 
     initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
 
-    execContexts[0]->setIntReg(ArgumentReg0, argc);
-    execContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
-    execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
+    threadContexts[0]->setIntReg(ArgumentReg0, argc);
+    threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
 
     Addr prog_entry = objFile->entryPoint();
-    execContexts[0]->setPC(prog_entry);
-    execContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
-    execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
+    threadContexts[0]->setPC(prog_entry);
+    threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+    threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
 
 //    num_processes++;
 }
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcLiveProcess)
-
-    VectorParam<string> cmd;
-    Param<string> executable;
-    Param<string> input;
-    Param<string> output;
-    VectorParam<string> env;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SparcLiveProcess)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SparcLiveProcess)
-
-    INIT_PARAM(cmd, "command line (executable plus arguments)"),
-    INIT_PARAM(executable, "executable (overrides cmd[0] if set)"),
-    INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"),
-    INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"),
-    INIT_PARAM(env, "environment settings"),
-    INIT_PARAM(system, "system")
-
-END_INIT_SIM_OBJECT_PARAMS(SparcLiveProcess)
-
-
-CREATE_SIM_OBJECT(SparcLiveProcess)
-{
-    string in = input;
-    string out = output;
-
-    // initialize file descriptors to default: same as simulator
-    int stdin_fd, stdout_fd, stderr_fd;
-
-    if (in == "stdin" || in == "cin")
-        stdin_fd = STDIN_FILENO;
-    else
-        stdin_fd = Process::openInputFile(input);
-
-    if (out == "stdout" || out == "cout")
-        stdout_fd = STDOUT_FILENO;
-    else if (out == "stderr" || out == "cerr")
-        stdout_fd = STDERR_FILENO;
-    else
-        stdout_fd = Process::openOutputFile(out);
-
-    stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO;
-
-    return SparcLiveProcess::create(getInstanceName(), system,
-                               stdin_fd, stdout_fd, stderr_fd,
-                               (string)executable == "" ? cmd[0] : executable,
-                               cmd, env);
-}
-
-
-REGISTER_SIM_OBJECT("SparcLiveProcess", SparcLiveProcess)
-
-
diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index c177f20a5..7ba8d7109 100644
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #ifndef __SPARC_PROCESS_HH__
@@ -62,15 +65,6 @@ class SparcLiveProcess : public LiveProcess
     void startup();
 
   public:
-    // this function is used to create the LiveProcess object, since
-    // we can't tell which subclass of LiveProcess to use until we
-    // open and look at the object file.
-    static SparcLiveProcess *create(const std::string &nm,
-                               System *_system,
-                               int stdin_fd, int stdout_fd, int stderr_fd,
-                               std::string executable,
-                               std::vector<std::string> &argv,
-                               std::vector<std::string> &envp);
 
     void argsInit(int intSize, int pageSize);
 
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 96f36eb91..cbeb3c7b9 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -24,14 +24,19 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #ifndef __ARCH_SPARC_REGFILE_HH__
 #define __ARCH_SPARC_REGFILE_HH__
 
+#include "arch/sparc/exceptions.hh"
 #include "arch/sparc/faults.hh"
 #include "base/trace.hh"
 #include "sim/byteswap.hh"
+#include "cpu/cpuevent.hh"
 #include "sim/host.hh"
 
 class Checkpoint;
@@ -42,7 +47,7 @@ namespace SparcISA
     typedef uint8_t  RegIndex;
 
     // MAXTL - maximum trap level
-    const int MaxPTL = 6;
+    const int MaxPTL = 2;
     const int MaxTL  = 6;
     const int MaxGL  = 3;
     const int MaxPGL = 2;
@@ -50,6 +55,14 @@ namespace SparcISA
     // NWINDOWS - number of register windows, can be 3 to 32
     const int NWindows = 32;
 
+
+    const int AsrStart = 0;
+    const int PrStart = 32;
+    const int HprStart = 64;
+    const int MiscStart = 96;
+
+    const uint64_t Bit64 = (1ULL << 63);
+
     class IntRegFile
     {
       protected:
@@ -231,17 +244,22 @@ namespace SparcISA
             //In each of these cases, we have to copy the value into a temporary
             //variable. This is because we may otherwise try to access an
             //unaligned portion of memory.
+
+            uint32_t result32;
+            uint64_t result64;
             switch(width)
             {
               case SingleWidth:
-                uint32_t result32 = gtoh((uint32_t)val);
+                result32 = gtoh((uint32_t)val);
                 memcpy(regSpace + 4 * floatReg, &result32, width);
+                break;
               case DoubleWidth:
-                uint64_t result64 = gtoh((uint64_t)val);
+                result64 = gtoh((uint64_t)val);
                 memcpy(regSpace + 4 * floatReg, &result64, width);
+                break;
               case QuadWidth:
-                uint64_t result128 = gtoh((uint64_t)val);
-                memcpy(regSpace + 4 * floatReg, &result128, width);
+                panic("Quad width FP not implemented.");
+                break;
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
             }
@@ -253,17 +271,21 @@ namespace SparcISA
             //In each of these cases, we have to copy the value into a temporary
             //variable. This is because we may otherwise try to access an
             //unaligned portion of memory.
+            uint32_t result32;
+            uint64_t result64;
             switch(width)
             {
               case SingleWidth:
-                uint32_t result32 = gtoh((uint32_t)val);
+                result32 = gtoh((uint32_t)val);
                 memcpy(regSpace + 4 * floatReg, &result32, width);
+                break;
               case DoubleWidth:
-                uint64_t result64 = gtoh((uint64_t)val);
+                result64 = gtoh((uint64_t)val);
                 memcpy(regSpace + 4 * floatReg, &result64, width);
+                break;
               case QuadWidth:
-                uint64_t result128 = gtoh((uint64_t)val);
-                memcpy(regSpace + 4 * floatReg, &result128, width);
+                panic("Quad width FP not implemented.");
+                break;
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
             }
@@ -277,156 +299,83 @@ namespace SparcISA
 
     enum MiscRegIndex
     {
-        MISCREG_PSTATE,
-        MISCREG_PSTATE_AG,
-        MISCREG_PSTATE_IE,
-        MISCREG_PSTATE_PRIV,
-        MISCREG_PSTATE_AM,
-        MISCREG_PSTATE_PEF,
-        MISCREG_PSTATE_RED,
-        MISCREG_PSTATE_MM,
-        MISCREG_PSTATE_TLE,
-        MISCREG_PSTATE_CLE,
-        MISCREG_TBA,
-        MISCREG_Y,
-        MISCREG_Y_VALUE,
-        MISCREG_PIL,
-        MISCREG_CWP,
-        MISCREG_TT_BASE,
-        MISCREG_TT_END = MISCREG_TT_BASE + MaxTL,
-        MISCREG_CCR,
-        MISCREG_CCR_ICC,
-        MISCREG_CCR_ICC_C,
-        MISCREG_CCR_ICC_V,
-        MISCREG_CCR_ICC_Z,
-        MISCREG_CCR_ICC_N,
-        MISCREG_CCR_XCC,
-        MISCREG_CCR_XCC_C,
-        MISCREG_CCR_XCC_V,
-        MISCREG_CCR_XCC_Z,
-        MISCREG_CCR_XCC_N,
-        MISCREG_ASI,
-        MISCREG_TL,
-        MISCREG_TPC_BASE,
-        MISCREG_TPC_END = MISCREG_TPC_BASE + MaxTL,
-        MISCREG_TNPC_BASE,
-        MISCREG_TNPC_END = MISCREG_TNPC_BASE + MaxTL,
-        MISCREG_TSTATE_BASE,
-        MISCREG_TSTATE_END = MISCREG_TSTATE_BASE + MaxTL,
-        MISCREG_TSTATE_CWP_BASE,
-        MISCREG_TSTATE_CWP_END = MISCREG_TSTATE_CWP_BASE + MaxTL,
-        MISCREG_TSTATE_PSTATE_BASE,
-        MISCREG_TSTATE_PSTATE_END = MISCREG_TSTATE_PSTATE_BASE + MaxTL,
-        MISCREG_TSTATE_ASI_BASE,
-        MISCREG_TSTATE_ASI_END = MISCREG_TSTATE_ASI_BASE + MaxTL,
-        MISCREG_TSTATE_CCR_BASE,
-        MISCREG_TSTATE_CCR_END = MISCREG_TSTATE_CCR_BASE + MaxTL,
-        MISCREG_TICK,
-        MISCREG_TICK_COUNTER,
-        MISCREG_TICK_NPT,
-        MISCREG_CANSAVE,
-        MISCREG_CANRESTORE,
-        MISCREG_OTHERWIN,
-        MISCREG_CLEANWIN,
-        MISCREG_WSTATE,
-        MISCREG_WSTATE_NORMAL,
-        MISCREG_WSTATE_OTHER,
-        MISCREG_VER,
-        MISCREG_VER_MAXWIN,
-        MISCREG_VER_MAXTL,
-        MISCREG_VER_MASK,
-        MISCREG_VER_IMPL,
-        MISCREG_VER_MANUF,
-        MISCREG_FSR,
-        MISCREG_FSR_CEXC,
-        MISCREG_FSR_CEXC_NXC,
-        MISCREG_FSR_CEXC_DZC,
-        MISCREG_FSR_CEXC_UFC,
-        MISCREG_FSR_CEXC_OFC,
-        MISCREG_FSR_CEXC_NVC,
-        MISCREG_FSR_AEXC,
-        MISCREG_FSR_AEXC_NXC,
-        MISCREG_FSR_AEXC_DZC,
-        MISCREG_FSR_AEXC_UFC,
-        MISCREG_FSR_AEXC_OFC,
-        MISCREG_FSR_AEXC_NVC,
-        MISCREG_FSR_FCC0,
-        MISCREG_FSR_QNE,
-        MISCREG_FSR_FTT,
-        MISCREG_FSR_VER,
-        MISCREG_FSR_NS,
-        MISCREG_FSR_TEM,
-        MISCREG_FSR_TEM_NXM,
-        MISCREG_FSR_TEM_DZM,
-        MISCREG_FSR_TEM_UFM,
-        MISCREG_FSR_TEM_OFM,
-        MISCREG_FSR_TEM_NVM,
-        MISCREG_FSR_RD,
-        MISCREG_FSR_FCC1,
-        MISCREG_FSR_FCC2,
-        MISCREG_FSR_FCC3,
-        MISCREG_FPRS,
-        MISCREG_FPRS_DL,
-        MISCREG_FPRS_DU,
-        MISCREG_FPRS_FEF,
-        numMiscRegs
+        /** Ancillary State Registers */
+        MISCREG_Y  = AsrStart + 0,
+        MISCREG_CCR = AsrStart + 2,
+        MISCREG_ASI = AsrStart + 3,
+        MISCREG_TICK = AsrStart + 4,
+        MISCREG_PC = AsrStart + 5,
+        MISCREG_FPRS = AsrStart + 6,
+        MISCREG_PCR = AsrStart + 16,
+        MISCREG_PIC = AsrStart + 17,
+        MISCREG_GSR = AsrStart + 19,
+        MISCREG_SOFTINT_SET = AsrStart + 20,
+        MISCREG_SOFTINT_CLR = AsrStart + 21,
+        MISCREG_SOFTINT = AsrStart + 22,
+        MISCREG_TICK_CMPR = AsrStart + 23,
+        MISCREG_STICK = AsrStart + 24,
+        MISCREG_STICK_CMPR = AsrStart + 25,
+
+        /** Privilged Registers */
+        MISCREG_TPC = PrStart + 0,
+        MISCREG_TNPC = PrStart + 1,
+        MISCREG_TSTATE = PrStart + 2,
+        MISCREG_TT = PrStart + 3,
+        MISCREG_PRIVTICK = PrStart + 4,
+        MISCREG_TBA = PrStart + 5,
+        MISCREG_PSTATE = PrStart + 6,
+        MISCREG_TL = PrStart + 7,
+        MISCREG_PIL = PrStart + 8,
+        MISCREG_CWP = PrStart + 9,
+        MISCREG_CANSAVE = PrStart + 10,
+        MISCREG_CANRESTORE = PrStart + 11,
+        MISCREG_CLEANWIN = PrStart + 12,
+        MISCREG_OTHERWIN = PrStart + 13,
+        MISCREG_WSTATE = PrStart + 14,
+        MISCREG_GL = PrStart + 16,
+
+        /** Hyper privileged registers */
+        MISCREG_HPSTATE = HprStart + 0,
+        MISCREG_HTSTATE = HprStart + 1,
+        MISCREG_HINTP = HprStart + 3,
+        MISCREG_HTBA = HprStart + 5,
+        MISCREG_HVER = HprStart + 6,
+        MISCREG_STRAND_STS_REG = HprStart + 16,
+        MISCREG_HSTICK_CMPR = HprStart + 31,
+
+        /** Floating Point Status Register */
+        MISCREG_FSR = MiscStart + 0
+
     };
 
     // The control registers, broken out into fields
     class MiscRegFile
     {
       private:
-        union
-        {
-            uint16_t pstate;		// Process State Register
-            struct
-            {
-                uint16_t ag:1;		// Alternate Globals
-                uint16_t ie:1;		// Interrupt enable
-                uint16_t priv:1;	// Privelege mode
-                uint16_t am:1;		// Address mask
-                uint16_t pef:1;		// PSTATE enable floating-point
-                uint16_t red:1;		// RED (reset, error, debug) state
-                uint16_t mm:2;		// Memory Model
-                uint16_t tle:1;		// Trap little-endian
-                uint16_t cle:1;		// Current little-endian
-            } pstateFields;
-        };
-        uint64_t tba;		// Trap Base Address
-        union
-        {
+
+        /* ASR Registers */
+        union {
             uint64_t y;		// Y (used in obsolete multiplication)
-            struct
-            {
+            struct {
                 uint64_t value:32;	// The actual value stored in y
                 uint64_t :32;	// reserved bits
             } yFields;
         };
-        uint8_t pil;		// Process Interrupt Register
-        uint8_t cwp;		// Current Window Pointer
-        uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured
-                                // on the previous level)
-        union
-        {
+        union {
             uint8_t	ccr;		// Condition Code Register
-            struct
-            {
-                union
-                {
+            struct {
+                union {
                     uint8_t icc:4;	// 32-bit condition codes
-                    struct
-                    {
+                    struct {
                         uint8_t c:1;	// Carry
                         uint8_t v:1;	// Overflow
                         uint8_t z:1;	// Zero
                         uint8_t n:1;	// Negative
                     } iccFields;
                 };
-                union
-                {
+                union {
                     uint8_t xcc:4;	// 64-bit condition codes
-                    struct
-                    {
+                    struct {
                         uint8_t c:1;	// Carry
                         uint8_t v:1;	// Overflow
                         uint8_t z:1;	// Zero
@@ -436,73 +385,143 @@ namespace SparcISA
             } ccrFields;
         };
         uint8_t asi;		// Address Space Identifier
-        uint8_t tl;		// Trap Level
+        union {
+            uint64_t tick;		// Hardware clock-tick counter
+            struct {
+                int64_t counter:63;	// Clock-tick count
+                uint64_t npt:1;		// Non-priveleged trap
+            } tickFields;
+        };
+        union {
+            uint8_t		fprs;	// Floating-Point Register State
+            struct {
+                uint8_t dl:1;		// Dirty lower
+                uint8_t du:1;		// Dirty upper
+                uint8_t fef:1;		// FPRS enable floating-Point
+            } fprsFields;
+        };
+        union {
+            uint64_t softint;
+            struct {
+                uint64_t tm:1;
+                uint64_t int_level:14;
+                uint64_t sm:1;
+            } softintFields;
+        };
+        union {
+            uint64_t tick_cmpr;		// Hardware tick compare registers
+            struct {
+                uint64_t tick_cmpr:63;	// Clock-tick count
+                uint64_t int_dis:1;		// Non-priveleged trap
+            } tick_cmprFields;
+        };
+        union {
+            uint64_t stick;		// Hardware clock-tick counter
+            struct {
+                int64_t :63;	// Not used, storage in SparcSystem
+                uint64_t npt:1;		// Non-priveleged trap
+            } stickFields;
+        };
+        union {
+            uint64_t stick_cmpr;		// Hardware tick compare registers
+            struct {
+                uint64_t tick_cmpr:63;	// Clock-tick count
+                uint64_t int_dis:1;		// Non-priveleged trap
+            } stick_cmprFields;
+        };
+
+
+        /* Privileged Registers */
         uint64_t tpc[MaxTL];	// Trap Program Counter (value from
                                 // previous trap level)
         uint64_t tnpc[MaxTL];	// Trap Next Program Counter (value from
                                 // previous trap level)
-        union
-        {
+        union {
             uint64_t tstate[MaxTL];	// Trap State
-            struct
-            {
+            struct {
                 //Values are from previous trap level
                 uint64_t cwp:5;		// Current Window Pointer
-                uint64_t :2;	// Reserved bits
-                uint64_t pstate:10;	// Process State
-                uint64_t :6;	// Reserved bits
+                uint64_t :3;	// Reserved bits
+                uint64_t pstate:13;	// Process State
+                uint64_t :3;	// Reserved bits
                 uint64_t asi:8;		// Address Space Identifier
                 uint64_t ccr:8;		// Condition Code Register
+                uint64_t gl:8;		// Global level
             } tstateFields[MaxTL];
         };
-        union
-        {
-            uint64_t tick;		// Hardware clock-tick counter
-            struct
-            {
-                uint64_t counter:63;	// Clock-tick count
-                uint64_t npt:1;		// Non-priveleged trap
-            } tickFields;
+        uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured
+                                // on the previous level)
+        uint64_t tba;		// Trap Base Address
+
+        union {
+            uint16_t pstate;		// Process State Register
+            struct {
+                uint16_t :1;		// reserved
+                uint16_t ie:1;		// Interrupt enable
+                uint16_t priv:1;	// Privelege mode
+                uint16_t am:1;		// Address mask
+                uint16_t pef:1;		// PSTATE enable floating-point
+                uint16_t :1;		// reserved2
+                uint16_t mm:2;		// Memory Model
+                uint16_t tle:1;		// Trap little-endian
+                uint16_t cle:1;		// Current little-endian
+            } pstateFields;
         };
+        uint8_t tl;		// Trap Level
+        uint8_t pil;		// Process Interrupt Register
+        uint8_t cwp;		// Current Window Pointer
         uint8_t cansave;	// Savable windows
         uint8_t canrestore;	// Restorable windows
-        uint8_t otherwin;	// Other windows
         uint8_t cleanwin;	// Clean windows
-        union
-        {
+        uint8_t otherwin;	// Other windows
+        union {
             uint8_t wstate;		// Window State
-            struct
-            {
+            struct {
                 uint8_t normal:3;	// Bits TT<4:2> are set to on a normal
                                         // register window trap
                 uint8_t other:3;	// Bits TT<4:2> are set to on an "otherwin"
                                         // register window trap
             } wstateFields;
         };
-        union
-        {
-            uint64_t ver;		// Version
-            struct
-            {
-                uint64_t maxwin:5;	// Max CWP value
-                uint64_t :2;	// Reserved bits
-                uint64_t maxtl:8;	// Maximum trap level
-                uint64_t :8;	// Reserved bits
-                uint64_t mask:8;	// Processor mask set revision number
-                uint64_t impl:16;	// Implementation identification number
-                uint64_t manuf:16;	// Manufacturer code
-            } verFields;
+        uint8_t gl;             // Global level register
+
+
+        /** Hyperprivileged Registers */
+        union {
+            uint64_t hpstate; // Hyperprivileged State Register
+            struct {
+                uint8_t tlz: 1;
+                uint8_t :1;
+                uint8_t hpriv:1;
+                uint8_t :2;
+                uint8_t red:1;
+                uint8_t :4;
+                uint8_t ibe:1;
+                uint8_t id:1;
+            } hpstateFields;
         };
-        union
-        {
+
+        uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
+        uint64_t hintp;
+        uint64_t htba; // Hyperprivileged Trap Base Address register
+        union {
+            uint64_t hstick_cmpr;		// Hardware tick compare registers
+            struct {
+                uint64_t tick_cmpr:63;	// Clock-tick count
+                uint64_t int_dis:1;		// Non-priveleged trap
+            } hstick_cmprFields;
+        };
+
+        uint64_t strandStatusReg; // Per strand status register
+
+
+        /** Floating point misc registers. */
+        union {
             uint64_t	fsr;	// Floating-Point State Register
-            struct
-            {
-                union
-                {
+            struct {
+                union {
                     uint64_t cexc:5;	// Current excpetion
-                    struct
-                    {
+                    struct {
                         uint64_t nxc:1;		// Inexact
                         uint64_t dzc:1;		// Divide by zero
                         uint64_t ufc:1;		// Underflow
@@ -510,11 +529,9 @@ namespace SparcISA
                         uint64_t nvc:1;		// Invalid operand
                     } cexcFields;
                 };
-                union
-                {
+                union {
                     uint64_t aexc:5;		// Accrued exception
-                    struct
-                    {
+                    struct {
                         uint64_t nxc:1;		// Inexact
                         uint64_t dzc:1;		// Divide by zero
                         uint64_t ufc:1;		// Underflow
@@ -530,11 +547,9 @@ namespace SparcISA
                 uint64_t ver:3;			// Version (of the FPU)
                 uint64_t :2;		// Reserved bits
                 uint64_t ns:1;			// Nonstandard floating point
-                union
-                {
+                union {
                     uint64_t tem:5;			// Trap Enable Mask
-                    struct
-                    {
+                    struct {
                         uint64_t nxm:1;		// Inexact
                         uint64_t dzm:1;		// Divide by zero
                         uint64_t ufm:1;		// Underflow
@@ -550,17 +565,34 @@ namespace SparcISA
                 uint64_t :26;		// Reserved bits
             } fsrFields;
         };
-        union
-        {
-            uint8_t		fprs;	// Floating-Point Register State
-            struct
-            {
-                uint8_t dl:1;		// Dirty lower
-                uint8_t du:1;		// Dirty upper
-                uint8_t fef:1;		// FPRS enable floating-Point
-            } fprsFields;
-        };
 
+        // These need to check the int_dis field and if 0 then
+        // set appropriate bit in softint and checkinterrutps on the cpu
+#if FULL_SYSTEM
+        /** Process a tick compare event and generate an interrupt on the cpu if
+         * appropriate. */
+        void processTickCompare(ThreadContext *tc);
+        void processSTickCompare(ThreadContext *tc);
+        void processHSTickCompare(ThreadContext *tc);
+
+        typedef CpuEventWrapper<MiscRegFile,
+                &MiscRegFile::processTickCompare> TickCompareEvent;
+        TickCompareEvent *tickCompare;
+
+        typedef CpuEventWrapper<MiscRegFile,
+                &MiscRegFile::processSTickCompare> STickCompareEvent;
+        STickCompareEvent *sTickCompare;
+
+        typedef CpuEventWrapper<MiscRegFile,
+                &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
+        HSTickCompareEvent *hSTickCompare;
+
+        /** Fullsystem only register version of ReadRegWithEffect() */
+        MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+        /** Fullsystem only register version of SetRegWithEffect() */
+        Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
+                ThreadContext * tc);
+#endif
       public:
 
         void reset()
@@ -572,18 +604,32 @@ namespace SparcISA
             //on reset Trap which sets the processor into the following state.
             //Bits that aren't set aren't defined on startup.
             tl = MaxTL;
-            tt[tl] = PowerOnReset.trapType();
-            pstateFields.mm = 0; //Total Store Order
-            pstateFields.red = 1; //Enter RED_State
-            pstateFields.am = 0; //Address Masking is turned off
-            pstateFields.priv = 1; //Processor enters privileged mode
-            pstateFields.ie = 0; //Interrupts are disabled
-            pstateFields.ag = 1; //Globals are replaced with alternate globals
-            pstateFields.tle = 0; //Big Endian mode for traps
-            pstateFields.cle = 0; //Big Endian mode for non-traps
-            tickFields.counter = 0; //The TICK register is unreadable by
-            tickFields.npt = 1; //The TICK register is unreadable by
-                                //non-priveleged software
+            gl = MaxGL;
+
+            tickFields.counter = 0; //The TICK register is unreadable bya
+            tickFields.npt = 1; //The TICK register is unreadable by by !priv
+
+            softint = 0; // Clear all the soft interrupt bits
+            tick_cmprFields.int_dis = 1; // disable timer compare interrupts
+            tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+            stickFields.npt = 1; //The TICK register is unreadable by by !priv
+            stick_cmprFields.int_dis = 1; // disable timer compare interrupts
+            stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+
+
+            tt[tl] = power_on_reset;
+            pstate = 0; // fields 0 but pef
+            pstateFields.pef = 1;
+
+            hpstate = 0;
+            hpstateFields.red = 1;
+            hpstateFields.hpriv = 1;
+            hpstateFields.tlz = 0; // this is a guess
+
+            hintp = 0; // no interrupts pending
+            hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
+            hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+
 #else
 /*	    //This sets up the initial state of the processor for usermode processes
             pstateFields.priv = 0; //Process runs in user mode
@@ -608,20 +654,42 @@ namespace SparcISA
             reset();
         }
 
+        /** read a value out of an either an SE or FS IPR. No checking is done
+         * about SE vs. FS as this is mostly used to copy the regfile. Thus more
+         * register are copied that are necessary for FS. However this prevents
+         * a bunch of ifdefs and is rarely called so is not performance
+         * criticial. */
         MiscReg readReg(int miscReg);
 
-        MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
-
+        /** Read a value from an IPR. Only the SE iprs are here and the rest
+         * are are readFSRegWithEffect (which is called by readRegWithEffect()).
+         * Checking is done for permission based on state bits in the miscreg
+         * file. */
+        MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+
+        /** write a value into an either an SE or FS IPR. No checking is done
+         * about SE vs. FS as this is mostly used to copy the regfile. Thus more
+         * register are copied that are necessary for FS. However this prevents
+         * a bunch of ifdefs and is rarely called so is not performance
+         * criticial.*/
         Fault setReg(int miscReg, const MiscReg &val);
 
+        /** Write a value into an IPR. Only the SE iprs are here and the rest
+         * are are setFSRegWithEffect (which is called by setRegWithEffect()).
+         * Checking is done for permission based on state bits in the miscreg
+         * file. */
         Fault setRegWithEffect(int miscReg,
-                const MiscReg &val, ExecContext * xc);
+                const MiscReg &val, ThreadContext * tc);
 
         void serialize(std::ostream & os);
 
         void unserialize(Checkpoint * cp, const std::string & section);
 
-        void copyMiscRegs(ExecContext * xc);
+        void copyMiscRegs(ThreadContext * tc);
+
+        bool isHyperPriv() { return hpstateFields.hpriv; }
+        bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
+        bool isNonPriv() { return !isPriv(); }
     };
 
     typedef union
@@ -693,9 +761,9 @@ namespace SparcISA
         }
 
         MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ExecContext *xc)
+                Fault &fault, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
         }
 
         Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -704,9 +772,9 @@ namespace SparcISA
         }
 
         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc)
+                ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+            return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg, int width)
@@ -775,22 +843,17 @@ namespace SparcISA
             CONTEXT_CWP,
             CONTEXT_GLOBALS
         };
-
-        union ContextVal
-        {
-            MiscReg reg;
-            int globalLevel;
-        };
+        typedef int ContextVal;
 
         void changeContext(ContextParam param, ContextVal val)
         {
             switch(param)
             {
               case CONTEXT_CWP:
-                intRegFile.setCWP(val.reg);
+                intRegFile.setCWP(val);
                 break;
               case CONTEXT_GLOBALS:
-                intRegFile.setGlobals(val.globalLevel);
+                intRegFile.setGlobals(val);
                 break;
               default:
                 panic("Tried to set illegal context parameter in the SPARC regfile.\n");
@@ -798,9 +861,11 @@ namespace SparcISA
         }
     };
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+    int InterruptLevel(uint64_t softint);
 
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc
index 95cdb0bd5..af0550910 100644
--- a/src/arch/sparc/solaris/process.cc
+++ b/src/arch/sparc/solaris/process.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #include "arch/sparc/isa_traits.hh"
@@ -31,7 +33,7 @@
 #include "arch/sparc/regfile.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/solaris/solaris.hh"
 
 #include "sim/process.hh"
@@ -44,9 +46,9 @@ using namespace SparcISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "SunOS");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -54,7 +56,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "Generic_118558-21");
     strcpy(name->machine, "sun4u");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
 
     return 0;
 }
diff --git a/src/arch/sparc/solaris/process.hh b/src/arch/sparc/solaris/process.hh
index 24dffdaf0..3c0d7eba7 100644
--- a/src/arch/sparc/solaris/process.hh
+++ b/src/arch/sparc/solaris/process.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #ifndef __SPARC_SOLARIS_PROCESS_HH__
diff --git a/src/arch/sparc/solaris/solaris.cc b/src/arch/sparc/solaris/solaris.cc
index a56f10740..c588925b0 100644
--- a/src/arch/sparc/solaris/solaris.cc
+++ b/src/arch/sparc/solaris/solaris.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #include "arch/sparc/solaris/solaris.hh"
diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh
index 6833a2d6a..0564faba4 100644
--- a/src/arch/sparc/solaris/solaris.hh
+++ b/src/arch/sparc/solaris/solaris.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #ifndef __ARCH_SPARC_SOLARIS_SOLARIS_HH__
diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh
index 1d8d97a79..d12aee211 100644
--- a/src/arch/sparc/stacktrace.hh
+++ b/src/arch/sparc/stacktrace.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
  */
 
 #ifndef __ARCH_ALPHA_STACKTRACE_HH__
@@ -32,13 +34,13 @@
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
-class ExecContext;
+class ThreadContext;
 class StackTrace;
 
 class ProcessInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
     int thread_info_size;
     int task_struct_size;
@@ -47,7 +49,7 @@ class ProcessInfo
     int name_off;
 
   public:
-    ProcessInfo(ExecContext *_xc);
+    ProcessInfo(ThreadContext *_tc);
 
     Addr task(Addr ksp) const;
     int pid(Addr ksp) const;
@@ -59,7 +61,7 @@ class StackTrace
   protected:
     typedef TheISA::MachInst MachInst;
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
     std::vector<Addr> stack;
 
   private:
@@ -68,21 +70,21 @@ class StackTrace
     bool decodeSave(MachInst inst, int &reg, int &disp);
     bool decodeStack(MachInst inst, int &disp);
 
-    void trace(ExecContext *xc, bool is_call);
+    void trace(ThreadContext *tc, bool is_call);
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
+    StackTrace(ThreadContext *tc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
     {
-        xc = 0;
+        tc = 0;
         stack.clear();
     }
 
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
+    bool valid() const { return tc != NULL; }
+    bool trace(ThreadContext *tc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -104,7 +106,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
@@ -112,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
     if (valid())
         clear();
 
-    trace(xc, !inst->isReturn());
+    trace(tc, !inst->isReturn());
     return true;
 }
 
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 1e2882607..e197e7918 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #include "arch/sparc/system.hh"
@@ -40,7 +42,8 @@
 using namespace BigEndianGuest;
 
 SparcSystem::SparcSystem(Params *p)
-    : System(p)
+    : System(p), sysTick(0)
+
 {
     resetSymtab = new SymbolTable;
     hypervisorSymtab = new SymbolTable;
diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index 27aa8768a..614707f6c 100644
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 #ifndef __ARCH_SPARC_SYSTEM_HH__
@@ -53,7 +55,7 @@ class SparcSystem : public System
 
     SparcSystem(Params *p);
 
-    ~SparcaSystem();
+    ~SparcSystem();
 
     virtual bool breakpoint();
 
@@ -82,6 +84,9 @@ class SparcSystem : public System
     /** Object pointer for the openboot code */
     ObjectFile *openboot;
 
+    /** System Tick for syncronized tick across all cpus. */
+    Tick sysTick;
+
   protected:
     const Params *params() const { return (const Params *)_params; }
 
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
new file mode 100644
index 000000000..35ff08b43
--- /dev/null
+++ b/src/arch/sparc/tlb.hh
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_TLB_HH__
+#define __ARCH_SPARC_TLB_HH__
+
+
+#endif // __ARCH_SPARC_TLB_HH__
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
new file mode 100644
index 000000000..b89d48663
--- /dev/null
+++ b/src/arch/sparc/ua2005.cc
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "arch/sparc/regfile.hh"
+
+Fault
+SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
+        ThreadContext *tc)
+{
+    int64_t time;
+    SparcSystem *sys;
+    switch (miscReg) {
+        /** Full system only ASRs */
+        case MISCREG_SOFTINT:
+          if (isNonPriv())
+              return new PrivilegedOpcode;
+          // Check if we are going to interrupt because of something
+          int oldLevel = InterruptLevel(softint);
+          int newLevel = InterruptLevel(val);
+          setReg(miscReg, val);
+          if (newLevel > oldLevel)
+              ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
+              //tc->getCpuPtr()->checkInterrupts = true;
+          return NoFault;
+
+        case MISCREG_SOFTINT_CLR:
+          return setRegWithEffect(miscReg, ~val & softint, tc);
+        case MISCREG_SOFTINT_SET:
+          return setRegWithEffect(miscReg, val | softint, tc);
+
+        case MISCREG_TICK_CMPR:
+          if (isNonPriv())
+              return new PrivilegedOpcode;
+          if (tickCompare == NULL)
+              tickCompare = new TickCompareEvent(this, tc);
+          setReg(miscReg, val);
+          if (tick_cmprFields.int_dis && tickCompare.scheduled())
+                  tickCompare.deschedule();
+          time = tick_cmprFields.tick_cmpr - tickFields.counter;
+          if (!tick_cmprFields.int_dis && time > 0)
+              tickCompare.schedule(time * tc->getCpuPtr()->cycles(1));
+          return NoFault;
+
+        case MISCREG_STICK:
+          if (isNonPriv())
+              return new PrivilegedOpcode;
+          if (isPriv())
+              return new PrivilegedAction;
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+          assert(sys != NULL);
+          sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
+          stickFields.npt = val & Bit64 ? 1 : 0;
+          return NoFault;
+
+        case MISCREG_STICK_CMPR:
+          if (isNonPriv())
+              return new PrivilegedOpcode;
+          if (sTickCompare == NULL)
+              sTickCompare = new STickCompareEvent(this, tc);
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+          assert(sys != NULL);
+          setReg(miscReg, val);
+          if (stick_cmprFields.int_dis && sTickCompare.scheduled())
+                  sTickCompare.deschedule();
+          time = stick_cmprFields.tick_cmpr - sys->sysTick;
+          if (!stick_cmprFields.int_dis && time > 0)
+              sTickCompare.schedule(time * Clock::Int::ns);
+          return NoFault;
+
+        /** Fullsystem only Priv registers. */
+        case MISCREG_PIL:
+          if (FULL_SYSTEM) {
+              setReg(miscReg, val);
+              //tc->getCpuPtr()->checkInterrupts;
+               // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
+              return NoFault;
+          } else
+              panic("PIL not implemented for syscall emulation\n");
+
+        /** Hyper privileged registers */
+        case MISCREG_HPSTATE:
+        case MISCREG_HINTP:
+          setReg(miscReg, val);
+          return NoFault;
+        case MISCREG_HTSTATE:
+          if (tl == 0)
+              return new IllegalInstruction;
+          setReg(miscReg, val);
+          return NoFault;
+
+        case MISCREG_HTBA:
+          // clear lower 7 bits on writes.
+          setReg(miscReg, val & ULL(~0x7FFF));
+          return NoFault;
+
+        case MISCREG_STRAND_STS_REG:
+          setReg(miscReg, strandStatusReg);
+          return NoFault;
+        case MISCREG_HSTICK_CMPR:
+          if (isNonPriv())
+              return new PrivilegedOpcode;
+          if (hSTickCompare == NULL)
+              hSTickCompare = new HSTickCompareEvent(this, tc);
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+          assert(sys != NULL);
+          setReg(miscReg, val);
+          if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
+                  hSTickCompare.deschedule();
+          int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
+          if (!hstick_cmprFields.int_dis && time > 0)
+              hSTickCompare.schedule(time * Clock::Int::ns);
+          return NoFault;
+        default:
+          return new IllegalInstruction;
+    }
+}
+
+MiscReg
+MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
+{
+    switch (miscReg) {
+
+        /** Privileged registers. */
+        case MISCREG_SOFTINT:
+           if (isNonPriv()) {
+               fault = new PrivilegedOpcode;
+               return 0;
+           }
+           return readReg(miscReg);
+        case MISCREG_TICK_CMPR:
+           if (isNonPriv()) {
+               fault =  new PrivilegedOpcode;
+               return 0;
+           }
+           return readReg(miscReg);
+        case MISCREG_STICK:
+          SparcSystem *sys;
+          if (stickFields.npt && !isNonPriv()) {
+              fault = new PrivilegedAction;
+              return 0;
+          }
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+          assert(sys != NULL);
+          return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
+        case MISCREG_STICK_CMPR:
+           if (isNonPriv()) {
+               fault =  new PrivilegedOpcode;
+               return 0;
+           }
+           return readReg(miscReg);
+
+
+        /** Hyper privileged registers */
+        case MISCREG_HPSTATE:
+        case MISCREG_HINTP:
+          return readReg(miscReg);
+        case MISCREG_HTSTATE:
+          if (tl == 0) {
+              fault = new IllegalInstruction;
+              return 0;
+          }
+          return readReg(miscReg);
+
+        case MISCREG_HTBA:
+          return readReg(miscReg) & ULL(~0x7FFF);
+        case MISCREG_HVER:
+          return NWindows | MaxTL << 8 | MaxGL << 16;
+        case MISCREG_STRAND_STS_REG:
+          return strandStatusReg;
+        case MISCREG_HSTICK_CMPR:
+          return hstick_cmpr;
+
+        default:
+          fault = new IllegalInstruction;
+          return 0;
+    }
+}
+
+void
+MiscRegFile::processTickCompare(ThreadContext *tc)
+{
+    panic("tick compare not implemented\n");
+}
+
+void
+MiscRegFile::processSTickCompare(ThreadContext *tc)
+{
+    panic("tick compare not implemented\n");
+}
+
+void
+MiscRegFile::processHSTickCompare(ThreadContext *tc)
+{
+    panic("tick compare not implemented\n");
+}
+
+}; // namespace SparcISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 1e67b3370..f1c071148 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
  */
 
 #ifndef __ARCH_SPARC_UTILITY_HH__
@@ -79,10 +81,10 @@ namespace SparcISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
 
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
new file mode 100644
index 000000000..f7fd92c15
--- /dev/null
+++ b/src/arch/sparc/vtophys.cc
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Ali Saidi
+ */
+
+#include <string>
+
+#include "arch/alpha/ev5.hh"
+#include "arch/alpha/vtophys.hh"
+#include "base/chunk_generator.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "mem/vport.hh"
+
+using namespace std;
+using namespace AlphaISA;
+
+AlphaISA::PageTableEntry
+AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
+{
+    Addr level1_pte = ptbr + vaddr.level1();
+    AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
+    if (!level1.valid()) {
+        DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
+        return 0;
+    }
+
+    Addr level2_pte = level1.paddr() + vaddr.level2();
+    AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
+    if (!level2.valid()) {
+        DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
+        return 0;
+    }
+
+    Addr level3_pte = level2.paddr() + vaddr.level3();
+    AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
+    if (!level3.valid()) {
+        DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
+        return 0;
+    }
+    return level3;
+}
+
+Addr
+AlphaISA::vtophys(Addr vaddr)
+{
+    Addr paddr = 0;
+    if (AlphaISA::IsUSeg(vaddr))
+        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
+    else if (AlphaISA::IsK0Seg(vaddr))
+        paddr = AlphaISA::K0Seg2Phys(vaddr);
+    else
+        panic("vtophys: ptbr is not set on virtual lookup");
+
+    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
+
+    return paddr;
+}
+
+Addr
+AlphaISA::vtophys(ThreadContext *tc, Addr addr)
+{
+    AlphaISA::VAddr vaddr = addr;
+    Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
+    Addr paddr = 0;
+    //@todo Andrew couldn't remember why he commented some of this code
+    //so I put it back in. Perhaps something to do with gdb debugging?
+    if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
+        paddr = vaddr & ~ULL(1);
+    } else {
+        if (AlphaISA::IsK0Seg(vaddr)) {
+            paddr = AlphaISA::K0Seg2Phys(vaddr);
+        } else if (!ptbr) {
+            paddr = vaddr;
+        } else {
+            AlphaISA::PageTableEntry pte =
+                kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
+            if (pte.valid())
+                paddr = pte.paddr() | vaddr.offset();
+        }
+    }
+
+
+    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
+
+    return paddr;
+}
+
+
+void
+AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
+{
+    uint8_t *dst = (uint8_t *)dest;
+    VirtualPort *vp = tc->getVirtPort(tc);
+
+    vp->readBlob(src, dst, cplen);
+
+    tc->delVirtPort(vp);
+
+}
+
+void
+AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
+{
+    uint8_t *src = (uint8_t *)source;
+    VirtualPort *vp = tc->getVirtPort(tc);
+
+    vp->writeBlob(dest, src, cplen);
+
+    tc->delVirtPort(vp);
+}
+
+void
+AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
+{
+    int len = 0;
+    VirtualPort *vp = tc->getVirtPort(tc);
+
+    do {
+        vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
+        len++;
+    } while (len < maxlen && dst[len] != 0 );
+
+    tc->delVirtPort(vp);
+    dst[len] = 0;
+}
+
+void
+AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
+{
+    VirtualPort *vp = tc->getVirtPort(tc);
+    for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
+            gen.next())
+    {
+        vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
+        src += gen.size();
+    }
+    tc->delVirtPort(vp);
+}
diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
new file mode 100644
index 000000000..bf2b757d6
--- /dev/null
+++ b/src/arch/sparc/vtophys.hh
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ */
+
+#ifndef __ARCH_SPARC_VTOPHYS_H__
+#define __ARCH_SPARC_VTOPHYS_H__
+
+#include "arch/sparc/isa_traits.hh"
+
+class ThreadContext;
+class FunctionalPort;
+
+namespace SparcISA {
+
+PageTableEntry
+kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
+
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
+void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
+
+};
+#endif // __ARCH_SPARC_VTOPHYS_H__
+
author	Ali Saidi <saidi@eecs.umich.edu>	2006-07-05 20:30:45 -0400
committer	Ali Saidi <saidi@eecs.umich.edu>	2006-07-05 20:30:45 -0400
commit	b36796914af8bfc6729cc8a519e57572460e43e8 (patch)
tree	1886edde38b2da28cb45f4e13135b1993502f45d /src/arch
parent	f456360bbcd6e4e4fd1550e96658934affac3eb9 (diff)
parent	4201ec84b2dd7d96148bf661124dd7b5d0e7204b (diff)
download	gem5-b36796914af8bfc6729cc8a519e57572460e43e8.tar.xz