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authorAli Saidi <Ali.Saidi@ARM.com>2011-05-04 20:38:28 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-05-04 20:38:28 -0500
commitba8d64520edcecdba28879399523fa6557268e21 (patch)
tree1daffd72ae92eb733ba65cc10daa6826780bf906 /src/arch
parent13574d8b4ee0b8a6e1b5fc7f0feaf2e43952e3df (diff)
downloadgem5-ba8d64520edcecdba28879399523fa6557268e21.tar.xz
ARM: Add support for MP misc regs and broadcast flushes.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.cc55
-rw-r--r--src/arch/arm/miscregs.hh6
2 files changed, 44 insertions, 17 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f7334ca9b..a92813697 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -43,6 +43,7 @@
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
+#include "sim/system.hh"
namespace ArmISA
{
@@ -191,6 +192,12 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
miscRegName[misc_reg]);
switch (misc_reg) {
+ case MISCREG_MPIDR:
+ return tc->cpuId();
+ break;
+ case MISCREG_ID_MMFR3:
+ return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
+ // BP Maint | Cache Maint Set/way | Cache Maint MVA
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
break;
@@ -244,6 +251,10 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
MiscReg newVal = val;
+ int x;
+ System *sys;
+ ThreadContext *oc;
+
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
@@ -351,9 +362,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
return;
case MISCREG_TLBIALLIS:
case MISCREG_TLBIALL:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushAll();
- tc->getDTBPtr()->flushAll();
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushAll();
+ oc->getDTBPtr()->flushAll();
+ }
return;
case MISCREG_ITLBIALL:
tc->getITBPtr()->flushAll();
@@ -363,23 +378,35 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
return;
case MISCREG_TLBIMVAIS:
case MISCREG_TLBIMVA:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
- bits(newVal, 7,0));
- tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
- bits(newVal, 7,0));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ }
return;
case MISCREG_TLBIASIDIS:
case MISCREG_TLBIASID:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
- tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
+ oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ }
return;
case MISCREG_TLBIMVAAIS:
case MISCREG_TLBIMVAA:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
- tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
+ oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ }
return;
case MISCREG_ITLBIMVA:
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 051cd490e..f87cc3ad5 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -149,6 +149,7 @@ namespace ArmISA
MISCREG_V2POWUR,
MISCREG_V2POWUW,
MISCREG_ID_MMFR0,
+ MISCREG_ID_MMFR3,
MISCREG_ACTLR,
MISCREG_PMCR,
MISCREG_PMCCNTR,
@@ -180,7 +181,6 @@ namespace ArmISA
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
- MISCREG_ID_MMFR3,
MISCREG_AIDR,
MISCREG_ADFSR,
MISCREG_AIFSR,
@@ -230,7 +230,7 @@ namespace ArmISA
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
- "id_mmfr0", "actlr", "pmcr", "pmccntr",
+ "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr",
"pmcntenset", "pmcntenclr", "pmovsr",
"pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr",
@@ -240,7 +240,7 @@ namespace ArmISA
// Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
- "id_mmfr1", "id_mmfr2", "id_mmfr3",
+ "id_mmfr1", "id_mmfr2",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",