Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/cpu/simple/base.cc:
    Hand merge

--HG--
extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d

7 files changed, 252 insertions, 24 deletions

diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
new file mode 100644
index 000000000..a19aeb763
--- /dev/null
+++ b/src/arch/alpha/AlphaSystem.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from System import System
+
+class AlphaSystem(System):
+    type = 'AlphaSystem'
+    console = Param.String("file that contains the console code")
+    pal = Param.String("file that contains palcode")
+    system_type = Param.UInt64("Type of system we are emulating")
+    system_rev = Param.UInt64("Revision of system we are emulating")
+
+class LinuxAlphaSystem(AlphaSystem):
+    type = 'LinuxAlphaSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+class FreebsdAlphaSystem(AlphaSystem):
+    type = 'FreebsdAlphaSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+class Tru64AlphaSystem(AlphaSystem):
+    type = 'Tru64AlphaSystem'
+    system_type = 12
+    system_rev = 2<<1
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
new file mode 100644
index 000000000..559516725
--- /dev/null
+++ b/src/arch/alpha/AlphaTLB.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+class AlphaTLB(SimObject):
+    type = 'AlphaTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+    type = 'AlphaDTB'
+    size = 64
+
+class AlphaITB(AlphaTLB):
+    type = 'AlphaITB'
+    size = 48
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 61611e9f6..2d59180c4 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha':
     Source('remote_gdb.cc')
 
     if env['FULL_SYSTEM']:
+        SimObject('AlphaSystem.py')
+        SimObject('AlphaTLB.py')
+
         Source('arguments.cc')
         Source('ev5.cc')
         Source('idle_event.cc')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index e342c79cf..c9dbb8cf2 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc':
     Source('remote_gdb.cc')
 
     if env['FULL_SYSTEM']:
+        SimObject('SparcSystem.py')
+        SimObject('SparcTLB.py')
+
         Source('arguments.cc')
         Source('pagetable.cc')
         Source('stacktrace.cc')
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
new file mode 100644
index 000000000..2e65f640d
--- /dev/null
+++ b/src/arch/sparc/SparcSystem.py
@@ -0,0 +1,74 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+
+from PhysicalMemory import *
+from System import System
+
+class SparcSystem(System):
+    type = 'SparcSystem'
+    _rom_base = 0xfff0000000
+    _nvram_base = 0x1f11000000
+    _hypervisor_desc_base = 0x1f12080000
+    _partition_desc_base = 0x1f12000000
+    # ROM for OBP/Reset/Hypervisor
+    rom = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_rom_base, size='8MB')),
+            "Memory to hold the ROM data")
+    # nvram
+    nvram = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')),
+        "Memory to hold the nvram data")
+    # hypervisor description
+    hypervisor_desc = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')),
+        "Memory to hold the hypervisor description")
+    # partition description
+    partition_desc = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')),
+        "Memory to hold the partition description")
+
+    reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
+    hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
+                                 "Address to load hypervisor at")
+    openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
+                               "Address to load openboot at")
+    nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
+    hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
+            "Address for the hypervisor description")
+    partition_desc_addr = Param.Addr(_partition_desc_base,
+            "Address for the partition description")
+
+    reset_bin = Param.String("file that contains the reset code")
+    hypervisor_bin = Param.String("file that contains the hypervisor code")
+    openboot_bin = Param.String("file that contains the openboot code")
+    nvram_bin = Param.String("file that contains the contents of nvram")
+    hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
+    partition_desc_bin = Param.String("file that contains the partition description")
+
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
new file mode 100644
index 000000000..30e5ebb08
--- /dev/null
+++ b/src/arch/sparc/SparcTLB.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.SimObject import SimObject
+from m5.params import *
+class SparcTLB(SimObject):
+    type = 'SparcTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class SparcDTB(SparcTLB):
+    type = 'SparcDTB'
+    size = 64
+
+class SparcITB(SparcTLB):
+    type = 'SparcITB'
+    size = 64
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index f511ef454..0300694cc 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -142,27 +142,38 @@ void MiscRegFile::clear()
 
 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
-    switch (miscReg) {
-      case MISCREG_TLB_DATA:
-        /* Package up all the data for the tlb:
-         * 6666555555555544444444443333333333222222222211111111110000000000
-         * 3210987654321098765432109876543210987654321098765432109876543210
-         *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
-         *                                                           ||||^red
-         *                                                           |||^priv
-         *                                                           ||^am
-         *                                                           |^lsuim
-         *                                                           ^lsudm
-         */
-        return bits((uint64_t)hpstate,2,2) |
-               bits((uint64_t)hpstate,5,5) << 1 |
-               bits((uint64_t)pstate,3,2) << 2 |
-               bits((uint64_t)lsuCtrlReg,3,2) << 4 |
-               bits((uint64_t)partId,7,0) << 8 |
-               bits((uint64_t)tl,2,0) << 16 |
-               (uint64_t)priContext << 32 |
-               (uint64_t)secContext << 48;
 
+  // The three miscRegs are moved up from the switch statement
+  // due to more frequent calls.
+
+  if (miscReg == MISCREG_GL)
+    return gl;
+  if (miscReg == MISCREG_CWP)
+    return cwp;
+  if (miscReg == MISCREG_TLB_DATA) {
+    /* Package up all the data for the tlb:
+     * 6666555555555544444444443333333333222222222211111111110000000000
+     * 3210987654321098765432109876543210987654321098765432109876543210
+     *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
+     *                                                           ||||^red
+     *                                                           |||^priv
+     *                                                           ||^am
+     *                                                           |^lsuim
+     *                                                           ^lsudm
+     */
+    return bits((uint64_t)hpstate,2,2) |
+           bits((uint64_t)hpstate,5,5) << 1 |
+           bits((uint64_t)pstate,3,2) << 2 |
+           bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+           bits((uint64_t)partId,7,0) << 8 |
+           bits((uint64_t)tl,2,0) << 16 |
+                (uint64_t)priContext << 32 |
+                (uint64_t)secContext << 48;
+  }
+
+    switch (miscReg) {
+      //case MISCREG_TLB_DATA:
+      //  [original contents see above]
       //case MISCREG_Y:
       //  return y;
       //case MISCREG_CCR:
@@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
         return tl;
       case MISCREG_PIL:
         return pil;
-      case MISCREG_CWP:
-        return cwp;
+      //CWP, GL moved
+      //case MISCREG_CWP:
+      //  return cwp;
       //case MISCREG_CANSAVE:
       //  return cansave;
       //case MISCREG_CANRESTORE:
@@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
       //  return otherwin;
       //case MISCREG_WSTATE:
       //  return wstate;
-      case MISCREG_GL:
-        return gl;
+      //case MISCREG_GL:
+      //  return gl;
 
         /** Hyper privileged registers */
       case MISCREG_HPSTATE: