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authorGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
commit8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7 (patch)
tree77126ed3bc26c1e36448b5e32b1da49b8f29b306 /src/arch
parentaf4c04c426cca3b73e58ab7464119db28252984c (diff)
downloadgem5-8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7.tar.xz
X86: Add some SSE floating point/integer conversion microops.
--HG-- extra : convert_revision : 2a1aa16709db940f5f40bbd84ca082f26b03b9c5
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa6
-rw-r--r--src/arch/x86/isa/insts/sse/__init__.py3
-rw-r--r--src/arch/x86/isa/insts/sse/convert.py86
-rw-r--r--src/arch/x86/isa/macroop.isa7
-rw-r--r--src/arch/x86/isa/microops/regop.isa19
5 files changed, 117 insertions, 4 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 6d5a04e2d..10b139fb9 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -201,8 +201,10 @@
}
// repne (0xF2)
0x8: decode OPCODE_OP_BOTTOM3 {
- 0x2: cvtsi2sd_Vq_Ed();
- 0x4: cvttsd2si_Gd_Wq();
+ // The size of the V operand should be q, not dp
+ 0x2: Inst::CVTSI2SD(Vdp,Edp);
+ // The size of the W operand should be q, not dp
+ 0x4: Inst::CVTTSD2SI(Gdp,Wdp);
0x5: cvtsd2si_Gd_Wq();
default: Inst::UD2();
}
diff --git a/src/arch/x86/isa/insts/sse/__init__.py b/src/arch/x86/isa/insts/sse/__init__.py
index c9469f17d..0377c3171 100644
--- a/src/arch/x86/isa/insts/sse/__init__.py
+++ b/src/arch/x86/isa/insts/sse/__init__.py
@@ -53,7 +53,8 @@
#
# Authors: Gabe Black
-categories = ["move"]
+categories = ["move",
+ "convert"]
microcode = '''
# SSE instructions
diff --git a/src/arch/x86/isa/insts/sse/convert.py b/src/arch/x86/isa/insts/sse/convert.py
new file mode 100644
index 000000000..070df84cc
--- /dev/null
+++ b/src/arch/x86/isa/insts/sse/convert.py
@@ -0,0 +1,86 @@
+# Copyright (c) 2007 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use of this software in source and binary forms,
+# with or without modification, are permitted provided that the
+# following conditions are met:
+#
+# The software must be used only for Non-Commercial Use which means any
+# use which is NOT directed to receiving any direct monetary
+# compensation for, or commercial advantage from such use. Illustrative
+# examples of non-commercial use are academic research, personal study,
+# teaching, education and corporate research & development.
+# Illustrative examples of commercial use are distributing products for
+# commercial advantage and providing services using the software for
+# commercial advantage.
+#
+# If you wish to use this software or functionality therein that may be
+# covered by patents for commercial use, please contact:
+# Director of Intellectual Property Licensing
+# Office of Strategy and Technology
+# Hewlett-Packard Company
+# 1501 Page Mill Road
+# Palo Alto, California 94304
+#
+# Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer. Redistributions
+# in binary form must reproduce the above copyright notice, this list of
+# conditions and the following disclaimer in the documentation and/or
+# other materials provided with the distribution. Neither the name of
+# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission. No right of
+# sublicense is granted herewith. Derivatives of the software and
+# output created using the software may be prepared, but only for
+# Non-Commercial Uses. Derivatives of the software may be shared with
+# others provided: (i) the others agree to abide by the list of
+# conditions herein which includes the Non-Commercial Use restrictions;
+# and (ii) such Derivatives of the software include the above copyright
+# notice to acknowledge the contribution from this software where
+# applicable, this list of conditions and the disclaimer below.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+microcode = '''
+def macroop CVTSI2SD_R_R {
+ cvtf_i2d xmml, regm
+};
+
+def macroop CVTSI2SD_R_M {
+ ld t1, seg, sib, disp
+ cvtf_i2d xmml, t1
+};
+
+def macroop CVTSI2SD_R_P {
+ rdip t7
+ ld t1, seg, riprel, disp
+ cvtf_i2d xmml, t1
+};
+
+def macroop CVTTSD2SI_R_R {
+ cvtf_d2i reg, xmmlm
+};
+
+def macroop CVTTSD2SI_R_M {
+ ldfp ufp1, seg, sib, disp
+ cvtf_d2i reg, ufp1
+};
+
+def macroop CVTTSD2SI_R_P {
+ rdip t7
+ ldfp ufp1, seg, riprel, disp
+ cvtf_d2i reg, ufp1
+};
+'''
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 3f33c8cfe..c9c33f981 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -221,6 +221,11 @@ let {{
self.dataSize = 1
elif self.size == 'd':
self.dataSize = 4
+ #This is for "double plus" which is normally a double word unless
+ #the REX W bit is set, in which case it's a quad word. It's used
+ #for some SSE instructions.
+ elif self.size == 'dp':
+ self.dataSize = "(REX_W ? 8 : 4)"
elif self.size == 'q':
self.dataSize = 8
elif self.size == 'v':
@@ -251,7 +256,7 @@ let {{
if not self.size:
self.size = size
else:
- if self.size is not size:
+ if self.size != size:
raise Exception, "Conflicting register sizes %s and %s!" %\
(self.size, size)
}};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index e169b09d2..3641438f5 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -636,4 +636,23 @@ let {{
class Zext(RegOp):
code = 'DestReg = bits(psrc1, imm8-1, 0);'
+
+ # Conversion microops
+ class ConvOp(RegOp):
+ abstract = True
+ def __init__(self, dest, src1):
+ super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS")
+
+ #FIXME This needs to always use 32 bits unless REX.W is present
+ class cvtf_i2d(ConvOp):
+ code = 'FpDestReg = psrc1;'
+
+ class cvtf_i2d_hi(ConvOp):
+ code = 'FpDestReg = bits(SrcReg1, 63, 32);'
+
+ class cvtf_d2i(ConvOp):
+ code = '''
+ int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
+ DestReg = merge(DestReg, intSrcReg1, dataSize);
+ '''
}};