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authorGabe Black <gblack@eecs.umich.edu>2009-11-10 21:10:18 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-11-10 21:10:18 -0800
commitb8120f6c38f212acbfd246a3081842a9e3d06eb3 (patch)
tree35ccdcab4455d39a3e89c078ba2875e57ba482ab /src/arch
parentbbbfdee2ed4feb5e8e448920e5d51701a2192ee1 (diff)
downloadgem5-b8120f6c38f212acbfd246a3081842a9e3d06eb3.tar.xz
Mem: Eliminate the NO_FAULT request flag.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/faults.cc2
-rw-r--r--src/arch/alpha/isa/decoder.isa2
-rw-r--r--src/arch/alpha/isa/mem.isa2
-rw-r--r--src/arch/mips/isa/formats/mem.isa2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index e93e16711..ff6de8d03 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc)
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
+ reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index cb43fcb74..52e124ad5 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -627,7 +627,7 @@ decode OPCODE default Unknown::unknown() {
format MiscPrefetch {
0xf800: wh64({{ EA = Rb & ~ULL(63); }},
{{ xc->writeHint(EA, 64, memAccessFlags); }},
- mem_flags = NO_FAULT,
+ mem_flags = PREFETCH,
inst_flags = [IsMemRef, IsDataPrefetch,
IsStore, MemWriteOp]);
}
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index fedfbf55d..b1703221f 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -548,7 +548,7 @@ def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
pf_flags = makeList(pf_flags)
inst_flags = makeList(inst_flags)
- pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+ pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
'IsDataPrefetch', 'MemReadOp']
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index adcb16137..161a52b06 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -619,7 +619,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
def format Prefetch(ea_code = {{ EA = Rs + disp; }},
mem_flags = [], pf_flags = [], inst_flags = []) {{
- pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+ pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
'IsDataPrefetch', 'MemReadOp']