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authorGabe Black <gblack@eecs.umich.edu>2007-07-30 13:25:00 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-30 13:25:00 -0700
commitda84aa95a99ef84ff10b7ce53156825e73d0b8e5 (patch)
treed815eb4f8ee8797f1de8e673987f466b1cb1731f /src/arch
parentd8beeff324f0d47927716e0081fe4a72c56601f7 (diff)
downloadgem5-da84aa95a99ef84ff10b7ce53156825e73d0b8e5.tar.xz
Make the register indices use the appropriate "fold" bit.
--HG-- extra : convert_revision : 89e15e2ef1f709f2c09238b78f94505ce8ef146d
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/operands.isa14
-rw-r--r--src/arch/x86/regfile.cc9
2 files changed, 14 insertions, 9 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 406c74a1f..127e1b98a 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,13 +96,13 @@ def operand_types {{
}};
def operands {{
- 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
- 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
- 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
- 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
- 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
- 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
- 'rax': ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7),
+ 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
+ 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
+ 'Base': ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3),
+ 'Index': ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4),
+ 'DestReg': ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
+ 'Data': ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
+ 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index f54f531e2..96283cada 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -86,6 +86,7 @@
*/
#include "arch/x86/regfile.hh"
+#include "base/trace.hh"
#include "sim/serialize.hh"
#include "cpu/thread_context.hh"
@@ -209,8 +210,12 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
{
- //For right now, don't do any flattening
- return reg;
+ //If we need to fold over the index to match byte semantics, do that.
+ //Otherwise, just strip off any extra bits and pass it through.
+ if (reg & (1 << 6))
+ return (reg & ~(1 << 6) - 0x4);
+ else
+ return (reg & ~(1 << 6));
}
void RegFile::serialize(std::ostream &os)