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authorGabe Black <gblack@eecs.umich.edu>2009-11-14 19:22:30 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-11-14 19:22:30 -0800
commite2ab64543b2a206c95fbf38565a50f0d5bba0f2a (patch)
tree8d9fc7020aa79adf1f6033bd974828525afd94de /src/arch
parent425ebf6bd736d6a7172476a81e935c7b83467dc9 (diff)
downloadgem5-e2ab64543b2a206c95fbf38565a50f0d5bba0f2a.tar.xz
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/miscregs.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 45233a764..d100efb8e 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -93,6 +93,10 @@ namespace ArmISA
Bitfield<4, 0> mode;
EndBitUnion(CPSR)
+ // This mask selects bits of the CPSR that actually go in the CondCodes
+ // integer register to allow renaming.
+ static const uint32_t CondCodesMask = 0xF80F0000;
+
BitUnion32(SCTLR)
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable