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| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | f4fd12d49e9a4aea3ab3b538301b5fd0f657137b (patch) | |
| tree | 6eb188a2f04f56c17061b21ec779095ab12c581a /src/arch | |
| parent | af8eb67fb44f7ab1831d6651ea4a079f2ebc99ff (diff) | |
| download | gem5-f4fd12d49e9a4aea3ab3b538301b5fd0f657137b.tar.xz | |
ARM: fix some cases where instructions that write to fp reg 15 are accidently branches.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 8 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 2ccda65e1..871378f3f 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1122,7 +1122,7 @@ def template LoadRegConstructor {{ #if %(use_uops)d assert(numMicroops >= 2); uops = new StaticInstPtr[numMicroops]; - if (_dest == INTREG_PC) { + if (_dest == INTREG_PC && !isFloating()) { IntRegIndex wbIndexReg = index; uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _shiftAmt, _shiftType, _index); @@ -1156,7 +1156,7 @@ def template LoadRegConstructor {{ } #else - if (_dest == INTREG_PC) { + if (_dest == INTREG_PC && !isFloating()) { flags[IsControl] = true; flags[IsIndirectControl] = true; if (conditional) @@ -1185,7 +1185,7 @@ def template LoadImmConstructor {{ #if %(use_uops)d assert(numMicroops >= 2); uops = new StaticInstPtr[numMicroops]; - if (_dest == INTREG_PC) { + if (_dest == INTREG_PC && !isFloating()) { uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _imm); uops[0]->setDelayedCommit(); @@ -1208,7 +1208,7 @@ def template LoadImmConstructor {{ uops[1]->setLastMicroop(); } #else - if (_dest == INTREG_PC) { + if (_dest == INTREG_PC && !isFloating()) { flags[IsControl] = true; flags[IsIndirectControl] = true; if (conditional) diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 918029cc2..42f515a3c 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -77,7 +77,7 @@ def template DataImmConstructor {{ } } - if (%(is_branch)s){ + if (%(is_branch)s && !isFloating()){ flags[IsControl] = true; flags[IsIndirectControl] = true; if (condCode == COND_AL || condCode == COND_UC) @@ -117,7 +117,7 @@ def template DataRegConstructor {{ } } - if (%(is_branch)s){ + if (%(is_branch)s && !isFloating()){ flags[IsControl] = true; flags[IsIndirectControl] = true; if (condCode == COND_AL || condCode == COND_UC) |