Clock: Move the clock and related functions to ClockedObject

This patch moves the clock of the CPU, bus, and numerous devices to
the new class ClockedObject, that sits in between the SimObject and
MemObject in the class hierarchy. Although there are currently a fair
amount of MemObjects that do not make use of the clock, they
potentially should do so, e.g. the caches should at some point have
the same clock as the CPU, potentially with a 1:n ratio. This patch
does not introduce any new clock objects or object hierarchies
(clusters, clock domains etc), but is still a step in the direction of
having a more structured approach clock domains.

The most contentious part of this patch is the serialisation of clocks
that some of the modules (but not all) did previously. This
serialisation should not be needed as the clock is set through the
parameters even when restoring from the checkpoint. In other words,
the state is "stored" in the Python code that creates the modules.

The nextCycle methods are also simplified and the clock phase
parameter of the CPU is removed (this could be part of a clock object
once they are introduced).

3 files changed, 5 insertions, 3 deletions

diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b418a7489..906903b8b 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -619,7 +619,6 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
 
 X86ISA::Interrupts::Interrupts(Params * p) :
     BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 
-    clock(0),
     apicTimerEvent(this),
     pendingSmi(false), smiVector(0),
     pendingNmi(false), nmiVector(0),
@@ -630,6 +629,8 @@ X86ISA::Interrupts::Interrupts(Params * p) :
     pendingIPIs(0), cpu(NULL),
     intSlavePort(name() + ".int_slave", this, this, latency)
 {
+    // Override the default clock
+    clock = 0;
     pioSize = PageBytes;
     memset(regs, 0, sizeof(regs));
     //Set the local apic DFR to the flat model.
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 1b7f5a52c..06425fbda 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -89,7 +89,6 @@ class Interrupts : public BasicPioDevice, IntDev
      * Timing related stuff.
      */
     Tick latency;
-    Tick clock;
 
     class ApicTimerEvent : public Event
     {
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 678467672..acca97c49 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -173,7 +173,9 @@ void initCPU(ThreadContext *tc, int cpuId)
     interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
 
     interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
-    
+
+    // @todo: Control the relative frequency, in this case 16:1, of
+    // the clocks in the Python code
     interrupts->setClock(tc->getCpuPtr()->ticks(16));
 
     // TODO Set the SMRAM base address (SMBASE) to 0x00030000