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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-10-31 01:21:54 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-10-31 01:21:54 -0400 |
commit | 538fae951b3a594814dff6bb6d038c32caadb25c (patch) | |
tree | a74245aab941fe20309c108d2e837e68ea5e4582 /src/arch | |
parent | 8ce31ea471eebb06efa590fb060804aa1fb5266b (diff) | |
download | gem5-538fae951b3a594814dff6bb6d038c32caadb25c.tar.xz |
Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/SConscript | 2 | ||||
-rw-r--r-- | src/arch/mips/SConscript | 2 | ||||
-rw-r--r-- | src/arch/sparc/SConscript | 1 | ||||
-rw-r--r-- | src/arch/x86/SConscript | 2 |
4 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 04bac3996..ca20cf585 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -75,3 +75,5 @@ if env['TARGET_ISA'] == 'alpha': for f in isa_desc_files: if not f.path.endswith('.hh'): Source(f) + + TraceFlag('Context') diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index e1d2146eb..f4be39eca 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -43,6 +43,8 @@ if env['TARGET_ISA'] == 'mips': SimObject('MipsTLB.py') + TraceFlag('MipsPRA') + if env['FULL_SYSTEM']: #Insert Full-System Files Here pass diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 81e96a8d6..a86c00250 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'sparc': Source('utility.cc') SimObject('SparcTLB.py') + TraceFlag('Sparc') if env['FULL_SYSTEM']: SimObject('SparcSystem.py') diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 3a94866bb..68a18d4c0 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -105,6 +105,8 @@ if env['TARGET_ISA'] == 'x86': Source('utility.cc') SimObject('X86TLB.py') + TraceFlag('Predecoder') + TraceFlag('X86') if env['FULL_SYSTEM']: SimObject('X86System.py') |