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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | 6365d29c21d474ddca551eb66b162e39e035f42c (patch) | |
| tree | c93ebc9bb1fa31147b04bd516875b108b2868d51 /src/arch | |
| parent | fbf2ad5ae84b88fc1505bfa16559b21aeb3520c1 (diff) | |
| download | gem5-6365d29c21d474ddca551eb66b162e39e035f42c.tar.xz | |
ARM: Decode the VMRS instruction.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index a51960641..7079631c7 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -255,9 +255,29 @@ def format ShortFpTransfer() {{ // A8-648 return new WarnUnimplemented("vmov", machInst); } else if (a == 7) { - // A8-658 - // B6-27 - return new WarnUnimplemented("vmrs", machInst); + const IntRegIndex rt = + (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + uint32_t specReg = bits(machInst, 19, 16); + switch (specReg) { + case 0: + specReg = MISCREG_FPSID; + break; + case 1: + specReg = MISCREG_FPSCR; + break; + case 6: + specReg = MISCREG_MVFR1; + break; + case 7: + specReg = MISCREG_MVFR0; + break; + case 8: + specReg = MISCREG_FPEXC; + break; + default: + return new Unknown(machInst); + } + return new Vmrs(machInst, rt, (IntRegIndex)specReg); } } else { // A8-646 |