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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
| commit | 8615b27174ae06db4665016c877b1e88031af203 (patch) | |
| tree | 7b28888f71e7e41e84d4087b6ccb53670e04582b /src/arch | |
| parent | 76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff) | |
| download | gem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz | |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa.cc | 5 | ||||
| -rw-r--r-- | src/arch/arm/vtophys.cc | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 6f66e5ae1..d3286a6b0 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1521,8 +1521,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); Request req(0, val, 1, flags, Request::funcMasterId, - tc->pcState().pc(), tc->contextId(), - tc->threadId()); + tc->pcState().pc(), tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); HCR hcr = readMiscRegNoEffect(MISCREG_HCR); @@ -1768,7 +1767,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); req->setVirt(0, val, 1, flags, Request::funcMasterId, tc->pcState().pc()); - req->setThreadContext(tc->contextId(), tc->threadId()); + req->setContext(tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType); diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc index 3aad35818..24fc5a5c7 100644 --- a/src/arch/arm/vtophys.cc +++ b/src/arch/arm/vtophys.cc @@ -69,7 +69,7 @@ try_translate(ThreadContext *tc, Addr addr) Fault fault; // Set up a functional memory Request to pass to the TLB // to get it to translate the vaddr to a paddr - Request req(0, addr, 64, 0x40, -1, 0, 0, 0); + Request req(0, addr, 64, 0x40, -1, 0, 0); ArmISA::TLB *tlb; // Check the TLBs for a translation |