diff options
| author | Gabe Black <gabeblack@google.com> | 2017-11-02 01:58:38 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-11-02 09:43:35 +0000 |
| commit | 8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch) | |
| tree | f791cd8adccee52d054f5a10b62948021a3d121b /src/arch | |
| parent | 97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff) | |
| download | gem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz | |
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
69 files changed, 328 insertions, 411 deletions
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index ea692aeef..36bfde2dd 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -42,7 +42,7 @@ output exec {{ /// instruction in full-system mode. /// @retval Full-system mode: NoFault if FP is enabled, FenFault /// if not. Non-full-system mode: always returns NoFault. - inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc) + inline Fault checkFpEnableFault(ExecContext *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { @@ -50,7 +50,7 @@ output exec {{ } return fault; } - inline Fault checkVectorEnableFault(CPU_EXEC_CONTEXT *xc) { + inline Fault checkVectorEnableFault(ExecContext *xc) { return std::make_shared<VectorEnableFault>(); } }}; @@ -206,7 +206,7 @@ output decoder {{ // FP instruction class execute method template. Handles non-standard // rounding modes. def template FloatingPointExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (trappingMode != Imprecise && !warnedOnTrapping) { @@ -250,7 +250,7 @@ def template FloatingPointExecute {{ // rounding mode control is needed. Like BasicExecute, but includes // check & warning for non-standard trapping mode. def template FPFixedRoundingExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (trappingMode != Imprecise && !warnedOnTrapping) { diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 34e2cb5ad..a6c9afe88 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -287,7 +287,7 @@ output decoder {{ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Basic instruction class declaration template. @@ -316,7 +316,7 @@ def template BasicConstructor {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -412,7 +412,7 @@ output decoder {{ output exec {{ Fault - Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const + Nop::execute(ExecContext *, Trace::InstRecord *) const { return NoFault; } diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index 6ba8ee5d0..5c76c263e 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -141,17 +141,16 @@ def template LoadStoreDeclare {{ def template EACompDeclare {{ - Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; }}; def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, - Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template LoadStoreConstructor {{ @@ -163,8 +162,8 @@ def template LoadStoreConstructor {{ }}; def template EACompExecute {{ - Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + Fault %(class_name)s::eaComp(ExecContext *xc, + Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -185,7 +184,7 @@ def template EACompExecute {{ def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -211,7 +210,7 @@ def template LoadExecute {{ def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -232,8 +231,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -257,7 +255,7 @@ def template LoadCompleteAcc {{ def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -290,7 +288,7 @@ def template StoreExecute {{ }}; def template StoreCondExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -324,7 +322,7 @@ def template StoreCondExecute {{ }}; def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -350,8 +348,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; @@ -360,8 +357,7 @@ def template StoreCompleteAcc {{ def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -385,7 +381,7 @@ def template StoreCondCompleteAcc {{ def template MiscExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA M5_VAR_USED; @@ -408,7 +404,7 @@ def template MiscExecute {{ // Prefetches in Alpha don't actually do anything // They just build an effective address and complete def template MiscInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { warn("initiateAcc undefined: Misc instruction does not support split " @@ -419,8 +415,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { warn("completeAcc undefined: Misc instruction does not support split " diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa index ceb25cd96..3ea56573a 100644 --- a/src/arch/alpha/isa/opcdec.isa +++ b/src/arch/alpha/isa/opcdec.isa @@ -66,8 +66,7 @@ output decoder {{ output exec {{ Fault - OpcdecFault::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + OpcdecFault::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return std::make_shared<UnimplementedOpcodeFault>(); } diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa index 26ec1c2bd..0446707bb 100644 --- a/src/arch/alpha/isa/unimp.isa +++ b/src/arch/alpha/isa/unimp.isa @@ -113,7 +113,7 @@ output decoder {{ output exec {{ Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " @@ -122,7 +122,7 @@ output exec {{ } Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (!warned) { diff --git a/src/arch/alpha/isa/unknown.isa b/src/arch/alpha/isa/unknown.isa index f356f24d8..7f5b9eb25 100644 --- a/src/arch/alpha/isa/unknown.isa +++ b/src/arch/alpha/isa/unknown.isa @@ -44,8 +44,7 @@ output decoder {{ output exec {{ Fault - Unknown::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unknown instruction " "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 486d30fe4..5c6a315a1 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -48,6 +48,7 @@ #include "arch/arm/utility.hh" #include "arch/arm/system.hh" #include "base/trace.hh" +#include "cpu/exec_context.hh" #include "cpu/static_inst.hh" #include "sim/byteswap.hh" #include "sim/full_system.hh" @@ -290,16 +291,14 @@ class ArmStaticInst : public StaticInst return ((spsr & ~bitMask) | (val & bitMask)); } - template<class XC> static inline Addr - readPC(XC *xc) + readPC(ExecContext *xc) { return xc->pcState().instPC(); } - template<class XC> static inline void - setNextPC(XC *xc, Addr val) + setNextPC(ExecContext *xc, Addr val) { PCState pc = xc->pcState(); pc.instNPC(val); @@ -340,9 +339,8 @@ class ArmStaticInst : public StaticInst } // Perform an interworking branch. - template<class XC> static inline void - setIWNextPC(XC *xc, Addr val) + setIWNextPC(ExecContext *xc, Addr val) { PCState pc = xc->pcState(); pc.instIWNPC(val); @@ -351,9 +349,8 @@ class ArmStaticInst : public StaticInst // Perform an interworking branch in ARM mode, a regular branch // otherwise. - template<class XC> static inline void - setAIWNextPC(XC *xc, Addr val) + setAIWNextPC(ExecContext *xc, Addr val) { PCState pc = xc->pcState(); pc.instAIWNPC(val); diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa index c55cdf6f6..69d6855e3 100644 --- a/src/arch/arm/isa/formats/breakpoint.isa +++ b/src/arch/arm/isa/formats/breakpoint.isa @@ -80,8 +80,7 @@ output decoder {{ output exec {{ Fault - Breakpoint::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + Breakpoint::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return std::make_shared<PrefetchAbort>(xc->pcState().pc(), ArmFault::DebugEvent); diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index 5faf9593a..c4c570bbe 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -42,7 +42,7 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Basic instruction class declaration template. @@ -82,7 +82,8 @@ def template BasicConstructor64 {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -110,7 +111,7 @@ def template BasicDecodeWithMnemonic {{ // Definitions of execute methods that panic. def template BasicExecPanic {{ -Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const +Fault execute(ExecContext *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); // GCC < 4.3 fail to recognize the above panic as no return diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index b252c91e7..05acb52eb 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -213,19 +213,19 @@ def template MicroIntConstructor {{ def template MicroNeonMemExecDeclare {{ template Fault %(class_name)s<%(targs)s>::execute( - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; template Fault %(class_name)s<%(targs)s>::initiateAcc( - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; template Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; }}; def template MicroNeonExecDeclare {{ template Fault %(class_name)s<%(targs)s>::execute( - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; }}; //////////////////////////////////////////////////////////////////// @@ -257,7 +257,7 @@ def template MicroNeonMixDeclare {{ def template MicroNeonMixExecute {{ template <class Element> - Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s<Element>::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index a0942d151..44f6ea797 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -42,7 +42,7 @@ def template PanicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("Execute function executed when it shouldn't be!\n"); @@ -51,7 +51,7 @@ def template PanicExecute {{ }}; def template PanicInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { panic("InitiateAcc function executed when it shouldn't be!\n"); @@ -60,8 +60,7 @@ def template PanicInitiateAcc {{ }}; def template PanicCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { panic("CompleteAcc function executed when it shouldn't be!\n"); @@ -71,7 +70,7 @@ def template PanicCompleteAcc {{ def template SwapExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -107,7 +106,7 @@ def template SwapExecute {{ }}; def template SwapInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -135,8 +134,7 @@ def template SwapInitiateAcc {{ }}; def template SwapCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -162,7 +160,7 @@ def template SwapCompleteAcc {{ }}; def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -193,7 +191,7 @@ def template LoadExecute {{ def template NeonLoadExecute {{ template <class Element> Fault %(class_name)s<Element>::execute( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -225,7 +223,7 @@ def template NeonLoadExecute {{ }}; def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -260,7 +258,7 @@ def template StoreExecute {{ def template NeonStoreExecute {{ template <class Element> Fault %(class_name)s<Element>::execute( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -296,7 +294,7 @@ def template NeonStoreExecute {{ }}; def template StoreExExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -335,7 +333,7 @@ def template StoreExExecute {{ }}; def template StoreExInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -364,7 +362,7 @@ def template StoreExInitiateAcc {{ }}; def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -395,7 +393,7 @@ def template StoreInitiateAcc {{ def template NeonStoreInitiateAcc {{ template <class Element> Fault %(class_name)s<Element>::initiateAcc( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -425,7 +423,7 @@ def template NeonStoreInitiateAcc {{ }}; def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -452,7 +450,7 @@ def template LoadInitiateAcc {{ def template NeonLoadInitiateAcc {{ template <class Element> Fault %(class_name)s<Element>::initiateAcc( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -476,8 +474,7 @@ def template NeonLoadInitiateAcc {{ }}; def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -506,7 +503,7 @@ def template LoadCompleteAcc {{ def template NeonLoadCompleteAcc {{ template <class Element> Fault %(class_name)s<Element>::completeAcc( - PacketPtr pkt, CPU_EXEC_CONTEXT *xc, + PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -534,8 +531,7 @@ def template NeonLoadCompleteAcc {{ }}; def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; @@ -545,16 +541,14 @@ def template StoreCompleteAcc {{ def template NeonStoreCompleteAcc {{ template <class Element> Fault %(class_name)s<Element>::completeAcc( - PacketPtr pkt, CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; } }}; def template StoreExCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -850,11 +844,11 @@ def template LoadImmDeclare {{ }}; def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template RfeConstructor {{ diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index e831f17a5..fc922b330 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -47,7 +47,7 @@ let {{ }}; def template Load64Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -71,7 +71,7 @@ def template Load64Execute {{ }}; def template Store64Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -99,7 +99,7 @@ def template Store64Execute {{ }}; def template Store64InitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -123,7 +123,7 @@ def template Store64InitiateAcc {{ }}; def template StoreEx64Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -156,7 +156,7 @@ def template StoreEx64Execute {{ }}; def template StoreEx64InitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -180,7 +180,7 @@ def template StoreEx64InitiateAcc {{ }}; def template Load64InitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -199,8 +199,7 @@ def template Load64InitiateAcc {{ }}; def template Load64CompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -224,8 +223,7 @@ def template Load64CompleteAcc {{ }}; def template Store64CompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; @@ -233,8 +231,7 @@ def template Store64CompleteAcc {{ }}; def template StoreEx64CompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -283,7 +280,7 @@ def template DCStore64Constructor {{ }}; def template DCStore64Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -311,7 +308,7 @@ def template DCStore64Execute {{ }}; def template DCStore64InitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 9e9b79957..c1ec74135 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -177,7 +177,7 @@ class %(class_name)s : public %(base_class)s def template NeonExecDeclare {{ template Fault %(class_name)s<%(targs)s>::execute( - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; }}; output header {{ @@ -208,7 +208,7 @@ output header {{ def template NeonEqualRegExecute {{ template <class Element> - Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s<Element>::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -253,7 +253,7 @@ output header {{ def template NeonUnequalRegExecute {{ template <class Element> - Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s<Element>::execute(ExecContext *xc, Trace::InstRecord *traceData) const { typedef typename bigger_type_t<Element>::type BigElement; diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index 336187fd8..f11ee91d4 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -167,12 +167,12 @@ class %(class_name)s : public %(base_class)s def template NeonXExecDeclare {{ template Fault %(class_name)s<%(targs)s>::execute( - CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; + ExecContext *, Trace::InstRecord *) const; }}; def template NeonXEqualRegOpExecute {{ template <class Element> - Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s<Element>::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -205,7 +205,7 @@ def template NeonXEqualRegOpExecute {{ def template NeonXUnequalRegOpExecute {{ template <class Element> - Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s<Element>::execute(ExecContext *xc, Trace::InstRecord *traceData) const { typedef typename bigger_type_t<Element>::type BigElement; @@ -275,7 +275,7 @@ def template MicroNeonMemDeclare64 {{ def template NeonLoadExecute64 {{ Fault %(class_name)s::execute( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -303,7 +303,7 @@ def template NeonLoadExecute64 {{ def template NeonLoadInitiateAcc64 {{ Fault %(class_name)s::initiateAcc( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -323,8 +323,7 @@ def template NeonLoadInitiateAcc64 {{ def template NeonLoadCompleteAcc64 {{ Fault %(class_name)s::completeAcc( - PacketPtr pkt, CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -349,7 +348,7 @@ def template NeonLoadCompleteAcc64 {{ def template NeonStoreExecute64 {{ Fault %(class_name)s::execute( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -381,7 +380,7 @@ def template NeonStoreExecute64 {{ def template NeonStoreInitiateAcc64 {{ Fault %(class_name)s::initiateAcc( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -407,8 +406,7 @@ def template NeonStoreInitiateAcc64 {{ def template NeonStoreCompleteAcc64 {{ Fault %(class_name)s::completeAcc( - PacketPtr pkt, CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; } @@ -505,7 +503,7 @@ def template MicroNeonMixLaneDeclare64 {{ }}; def template MicroNeonMixExecute64 {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 7b372bdee..fb0a404cb 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -165,7 +165,8 @@ def template DataRegRegConstructor {{ }}; def template PredOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; uint64_t resTemp = 0; @@ -189,7 +190,8 @@ def template PredOpExecute {{ }}; def template QuiescePredOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; uint64_t resTemp = 0; @@ -214,7 +216,8 @@ def template QuiescePredOpExecute {{ }}; def template QuiescePredOpExecuteWithFixup {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; uint64_t resTemp = 0; diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 7764c344c..fe95d06bf 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -122,8 +122,6 @@ class Template(object): # Protect non-Python-dict substitutions (e.g. if there's a printf # in the templated C++ code) template = self.parser.protectNonSubstPercents(self.template) - # CPU-model-specific substitutions are handled later (in GenCode). - template = self.parser.protectCpuSymbols(template) # Build a dict ('myDict') to use for the template substitution. # Start with the template namespace. Make a copy since we're @@ -218,11 +216,9 @@ class Template(object): raise TypeError, "Template.subst() arg must be or have dictionary" return template % myDict - # Convert to string. This handles the case when a template with a - # CPU-specific term gets interpolated into another template or into - # an output block. + # Convert to string. def __str__(self): - return self.parser.expandCpuSymbolsToString(self.template) + return self.template ################ # Format object. @@ -284,23 +280,18 @@ class NoFormat(object): # strings containing code destined for decoder.hh and decoder.cc # respectively. The decode_block attribute contains code to be # incorporated in the decode function itself (that will also end up in -# decoder.cc). The exec_output attribute is a dictionary with a key -# for each CPU model name; the value associated with a particular key -# is the string of code for that CPU model's exec.cc file. The -# has_decode_default attribute is used in the decode block to allow -# explicit default clauses to override default default clauses. +# decoder.cc). The exec_output attribute is the string of code for the +# exec.cc file. The has_decode_default attribute is used in the decode block +# to allow explicit default clauses to override default default clauses. class GenCode(object): - # Constructor. At this point we substitute out all CPU-specific - # symbols. For the exec output, these go into the per-model - # dictionary. For all other output types they get collapsed into - # a single string. + # Constructor. def __init__(self, parser, header_output = '', decoder_output = '', exec_output = '', decode_block = '', has_decode_default = False): self.parser = parser - self.header_output = parser.expandCpuSymbolsToString(header_output) - self.decoder_output = parser.expandCpuSymbolsToString(decoder_output) + self.header_output = header_output + self.decoder_output = decoder_output self.exec_output = exec_output self.decode_block = decode_block self.has_decode_default = has_decode_default @@ -1462,26 +1453,12 @@ class LineTracker(object): # class ISAParser(Grammar): - class CpuModel(object): - def __init__(self, name, filename, includes, strings): - self.name = name - self.filename = filename - self.includes = includes - self.strings = strings - def __init__(self, output_dir): super(ISAParser, self).__init__() self.output_dir = output_dir self.filename = None # for output file watermarking/scaremongering - self.cpuModels = [ - ISAParser.CpuModel('ExecContext', - 'generic_cpu_exec.cc', - '#include "cpu/exec_context.hh"', - { "CPU_exec_context" : "ExecContext" }), - ] - # variable to hold templates self.templateMap = {} @@ -1625,33 +1602,26 @@ class ISAParser(Grammar): print >>f, '#include "%s"' % fn print >>f, '}' - # instruction execution per-CPU model + # instruction execution splits = self.splits[self.get_file('exec')] - for cpu in self.cpuModels: - for i in range(1, splits+1): + for i in range(1, splits+1): + file = 'generic_cpu_exec.cc' + if splits > 1: + file = extn.sub(r'_%d\1' % i, file) + with self.open(file) as f: + fn = 'exec-g.cc.inc' + assert(fn in self.files) + f.write('#include "%s"\n' % fn) + f.write('#include "cpu/exec_context.hh"\n') + f.write('#include "decoder.hh"\n') + + fn = 'exec-ns.cc.inc' + assert(fn in self.files) + print >>f, 'namespace %s {' % self.namespace if splits > 1: - file = extn.sub(r'_%d\1' % i, cpu.filename) - else: - file = cpu.filename - with self.open(file) as f: - fn = 'exec-g.cc.inc' - assert(fn in self.files) - f.write('#include "%s"\n' % fn) - - f.write(cpu.includes+"\n") - - fn = 'decoder.hh' - f.write('#include "%s"\n' % fn) - - fn = 'exec-ns.cc.inc' - assert(fn in self.files) - print >>f, 'namespace %s {' % self.namespace - print >>f, '#define CPU_EXEC_CONTEXT %s' \ - % cpu.strings['CPU_exec_context'] - if splits > 1: - print >>f, '#define __SPLIT %u' % i - print >>f, '#include "%s"' % fn - print >>f, '}' + print >>f, '#define __SPLIT %u' % i + print >>f, '#include "%s"' % fn + print >>f, '}' # max_inst_regs.hh self.update('max_inst_regs.hh', @@ -1921,13 +1891,10 @@ class ISAParser(Grammar): # Massage output block by substituting in template definitions and # bit operators. We handle '%'s embedded in the string that don't - # indicate template substitutions (or CPU-specific symbols, which - # get handled in GenCode) by doubling them first so that the + # indicate template substitutions by doubling them first so that the # format operation will reduce them back to single '%'s. def process_output(self, s): s = self.protectNonSubstPercents(s) - # protects cpu-specific symbols too - s = self.protectCpuSymbols(s) return substBitOps(s % self.templateMap) def p_output(self, t): @@ -2426,40 +2393,6 @@ StaticInstPtr # create new object and store in global map self.formatMap[id] = Format(id, params, code) - def expandCpuSymbolsToDict(self, template): - '''Expand template with CPU-specific references into a - dictionary with an entry for each CPU model name. The entry - key is the model name and the corresponding value is the - template with the CPU-specific refs substituted for that - model.''' - - # Protect '%'s that don't go with CPU-specific terms - t = re.sub(r'%(?!\(CPU_)', '%%', template) - result = {} - for cpu in self.cpuModels: - result[cpu.name] = t % cpu.strings - return result - - def expandCpuSymbolsToString(self, template): - '''*If* the template has CPU-specific references, return a - single string containing a copy of the template for each CPU - model with the corresponding values substituted in. If the - template has no CPU-specific references, it is returned - unmodified.''' - - if template.find('%(CPU_') != -1: - return reduce(lambda x,y: x+y, - self.expandCpuSymbolsToDict(template).values()) - else: - return template - - def protectCpuSymbols(self, template): - '''Protect CPU-specific references by doubling the - corresponding '%'s (in preparation for substituting a different - set of references into the template).''' - - return re.sub(r'%(?=\(CPU_)', '%%', template) - def protectNonSubstPercents(self, s): '''Protect any non-dict-substitution '%'s in a format string (i.e. those not followed by '(')''' diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa index 98da450d8..7431b94f5 100644 --- a/src/arch/mips/isa/formats/basic.isa +++ b/src/arch/mips/isa/formats/basic.isa @@ -33,7 +33,7 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Basic instruction class declaration template. @@ -61,7 +61,8 @@ def template BasicConstructor {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index 123468287..00600712c 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -80,7 +80,8 @@ output header {{ // Basic instruction class execute method template. def template CP0Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -101,7 +102,8 @@ def template CP0Execute {{ }}; def template CP1Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -122,7 +124,8 @@ def template CP1Execute {{ }}; // Basic instruction class execute method template. def template ControlTLBExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -173,15 +176,15 @@ output decoder {{ }}; output header {{ - bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num); + bool isCoprocessorEnabled(ExecContext *xc, unsigned cop_num); - bool isMMUTLB(%(CPU_exec_context)s *xc); + bool isMMUTLB(ExecContext *xc); }}; output exec {{ bool - isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num) + isCoprocessorEnabled(ExecContext *xc, unsigned cop_num) { if (!FullSystem) return true; @@ -203,7 +206,7 @@ output exec {{ } bool inline - isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc) + isCoprocessor0Enabled(ExecContext *xc) { if (FullSystem) { MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); @@ -219,7 +222,7 @@ output exec {{ } bool - isMMUTLB(CPU_EXEC_CONTEXT *xc) + isMMUTLB(ExecContext *xc) { MiscReg Config = xc->readMiscReg(MISCREG_CONFIG); return FullSystem && (Config & 0x380) == 0x80; diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa index 2a946ed9d..78fb93063 100755 --- a/src/arch/mips/isa/formats/dsp.isa +++ b/src/arch/mips/isa/formats/dsp.isa @@ -64,7 +64,8 @@ output header {{ // Dsp instruction class execute method template. def template DspExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -97,7 +98,8 @@ def template DspExecute {{ // DspHiLo instruction class execute method template. def template DspHiLoExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -136,9 +138,9 @@ def template DspHiLoExecute {{ }}; output header {{ - bool isDspEnabled(%(CPU_exec_context)s *xc); + bool isDspEnabled(ExecContext *xc); - bool isDspPresent(%(CPU_exec_context)s *xc); + bool isDspPresent(ExecContext *xc); }}; //Outputs to decoder.cc @@ -147,7 +149,7 @@ output decoder {{ output exec {{ bool - isDspEnabled(CPU_EXEC_CONTEXT *xc) + isDspEnabled(ExecContext *xc) { return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24); } @@ -155,7 +157,7 @@ output exec {{ output exec {{ bool - isDspPresent(CPU_EXEC_CONTEXT *xc) + isDspPresent(ExecContext *xc) { return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10); } diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index c0dff477b..eb5e5765a 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -87,12 +87,12 @@ output decoder {{ }}; output header {{ - void fpResetCauseBits(%(CPU_exec_context)s *cpu); + void fpResetCauseBits(ExecContext *cpu); }}; output exec {{ - inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc) + inline Fault checkFpEnableFault(ExecContext *xc) { //@TODO: Implement correct CP0 checks to see if the CP1 // unit is enable or not @@ -105,7 +105,7 @@ output exec {{ //If any operand is Nan return the appropriate QNaN template <class T> bool - fpNanOperands(FPOp *inst, CPU_EXEC_CONTEXT *xc, const T &src_type, + fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; @@ -126,7 +126,7 @@ output exec {{ template <class T> bool - fpInvalidOp(FPOp *inst, CPU_EXEC_CONTEXT *cpu, const T dest_val, + fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; @@ -156,7 +156,7 @@ output exec {{ } void - fpResetCauseBits(CPU_EXEC_CONTEXT *cpu) + fpResetCauseBits(ExecContext *cpu) { //Read FCSR from FloatRegFile uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); @@ -170,7 +170,8 @@ output exec {{ }}; def template FloatingPointExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index c21c1255b..9f43ac275 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -133,7 +133,8 @@ output header {{ // HiLo instruction class execute method template. def template HiLoExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -152,7 +153,8 @@ def template HiLoExecute {{ // HiLoRsSel instruction class execute method template. def template HiLoRsSelExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -178,7 +180,8 @@ def template HiLoRsSelExecute {{ // HiLoRdSel instruction class execute method template. def template HiLoRdSelExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 052ead82c..9e5f538e6 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -97,7 +97,7 @@ output decoder {{ }}; output header {{ - uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet); + uint64_t getMemData(ExecContext *xc, Packet *packet); }}; @@ -105,7 +105,7 @@ output exec {{ /** return data in cases where there the size of data is only known in the packet */ - uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) { + uint64_t getMemData(ExecContext *xc, Packet *packet) { switch (packet->getSize()) { case 1: @@ -153,16 +153,16 @@ def template LoadStoreDeclare {{ }}; def template EACompDeclare {{ - Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; }}; def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; }}; def template LoadStoreConstructor {{ @@ -176,8 +176,7 @@ def template LoadStoreConstructor {{ def template EACompExecute {{ Fault - %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -203,7 +202,7 @@ def template EACompExecute {{ }}; def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -235,7 +234,7 @@ def template LoadExecute {{ def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -261,8 +260,7 @@ def template LoadInitiateAcc {{ }}; def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -292,7 +290,7 @@ def template LoadCompleteAcc {{ }}; def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -326,7 +324,7 @@ def template StoreExecute {{ def template StoreFPExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -361,7 +359,7 @@ def template StoreFPExecute {{ }}; def template StoreCondExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -395,7 +393,7 @@ def template StoreCondExecute {{ }}; def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -422,7 +420,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; @@ -431,7 +429,7 @@ def template StoreCompleteAcc {{ def template StoreCondCompleteAcc {{ Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -454,7 +452,7 @@ def template StoreCondCompleteAcc {{ }}; def template MiscExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA M5_VAR_USED = 0; @@ -474,7 +472,7 @@ def template MiscExecute {{ }}; def template MiscInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { panic("Misc instruction does not support split access method!"); @@ -484,8 +482,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const { panic("Misc instruction does not support split access method!"); diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index b34773ef5..b9ee07010 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -85,18 +85,18 @@ output decoder {{ }}; output header {{ - void getThrRegExValues(%(CPU_exec_context)s *xc, + void getThrRegExValues(ExecContext *xc, MipsISA::VPEConf0Reg &vpe_conf0, MipsISA::TCBindReg &tc_bind_mt, MipsISA::TCBindReg &tc_bind, MipsISA::VPEControlReg &vpe_control, MipsISA::MVPConf0Reg &mvp_conf0); - void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3); + void getMTExValues(ExecContext *xc, MipsISA::Config3Reg &config3); }}; output exec {{ - void getThrRegExValues(CPU_EXEC_CONTEXT *xc, + void getThrRegExValues(ExecContext *xc, VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, TCBindReg &tc_bind, VPEControlReg &vpe_control, MVPConf0Reg &mvp_conf0) @@ -109,14 +109,15 @@ output exec {{ mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); } - void getMTExValues(CPU_EXEC_CONTEXT *xc, Config3Reg &config3) + void getMTExValues(ExecContext *xc, Config3Reg &config3) { config3 = xc->readMiscReg(MISCREG_CONFIG3); } }}; def template ThreadRegisterExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; int64_t data M5_VAR_USED; @@ -154,7 +155,8 @@ def template ThreadRegisterExecute {{ }}; def template MTExecute{{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa index 5964b0f0a..17c653f14 100644 --- a/src/arch/mips/isa/formats/noop.isa +++ b/src/arch/mips/isa/formats/noop.isa @@ -82,7 +82,7 @@ output decoder {{ output exec {{ Fault - Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const + Nop::execute(ExecContext *, Trace::InstRecord *) const { return NoFault; } diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa index bd27a347c..4ec1d267e 100644 --- a/src/arch/mips/isa/formats/tlbop.isa +++ b/src/arch/mips/isa/formats/tlbop.isa @@ -58,7 +58,8 @@ output decoder {{ }}; def template TlbOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { //Write the resulting state to the execution context %(op_wb)s; diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa index 796cb5928..5133899ea 100644 --- a/src/arch/mips/isa/formats/trap.isa +++ b/src/arch/mips/isa/formats/trap.isa @@ -81,7 +81,8 @@ output decoder {{ def template TrapExecute {{ //Edit This Template When Traps Are Implemented - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { //Write the resulting state to the execution context %(op_wb)s; diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa index a51865584..6f573b667 100644 --- a/src/arch/mips/isa/formats/unimp.isa +++ b/src/arch/mips/isa/formats/unimp.isa @@ -180,7 +180,7 @@ output decoder {{ output exec {{ Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " @@ -190,7 +190,7 @@ output exec {{ } Fault - CP0Unimplemented::execute(CPU_EXEC_CONTEXT *xc, + CP0Unimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (FullSystem) { @@ -207,7 +207,7 @@ output exec {{ } Fault - CP1Unimplemented::execute(CPU_EXEC_CONTEXT *xc, + CP1Unimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (FullSystem) { @@ -224,7 +224,7 @@ output exec {{ } Fault - CP2Unimplemented::execute(CPU_EXEC_CONTEXT *xc, + CP2Unimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (FullSystem) { @@ -241,7 +241,7 @@ output exec {{ } Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (!warned) { diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa index fd6c9ea18..fb29eea4b 100644 --- a/src/arch/mips/isa/formats/unknown.isa +++ b/src/arch/mips/isa/formats/unknown.isa @@ -69,8 +69,7 @@ output decoder {{ output exec {{ Fault - Unknown::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return std::make_shared<ReservedInstructionFault>(); } diff --git a/src/arch/power/isa/formats/basic.isa b/src/arch/power/isa/formats/basic.isa index 75c9f94bc..e1885fa1b 100644 --- a/src/arch/power/isa/formats/basic.isa +++ b/src/arch/power/isa/formats/basic.isa @@ -30,7 +30,7 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Basic instruction class declaration template. @@ -58,7 +58,8 @@ def template BasicConstructor {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -87,7 +88,7 @@ def template BasicDecodeWithMnemonic {{ // Definitions of execute methods that panic. def template BasicExecPanic {{ -Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const +Fault execute(ExecContext *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); } diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index eafd6aea7..ca2d404f8 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -54,12 +54,12 @@ def template LoadStoreDeclare {{ def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; @@ -73,7 +73,7 @@ def template LoadStoreConstructor {{ def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -98,7 +98,7 @@ def template LoadExecute {{ def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -120,7 +120,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + ExecContext *xc, Trace::InstRecord *traceData) const { Addr M5_VAR_USED EA; @@ -147,7 +147,7 @@ def template LoadCompleteAcc {{ def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -176,7 +176,7 @@ def template StoreExecute {{ def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -206,8 +206,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; diff --git a/src/arch/power/isa/formats/misc.isa b/src/arch/power/isa/formats/misc.isa index 3d22b597e..af2c2de64 100644 --- a/src/arch/power/isa/formats/misc.isa +++ b/src/arch/power/isa/formats/misc.isa @@ -34,7 +34,8 @@ // def template MiscOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa index daee8f559..241e6218b 100644 --- a/src/arch/power/isa/formats/unimp.isa +++ b/src/arch/power/isa/formats/unimp.isa @@ -111,7 +111,7 @@ output decoder {{ output exec {{ Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " @@ -121,7 +121,7 @@ output exec {{ } Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (!warned) { diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa index d9985e7c6..9f08bc1ee 100644 --- a/src/arch/power/isa/formats/unknown.isa +++ b/src/arch/power/isa/formats/unknown.isa @@ -71,8 +71,7 @@ output decoder {{ output exec {{ Fault - Unknown::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unknown instruction at %#x" "(inst 0x%08x, opcode 0x%x, binary: %s)", diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index 24e13c984..983c1f4cc 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -223,7 +223,7 @@ def template AtomicMemOpStoreConstructor {{ }}; def template StoreCondExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -259,7 +259,7 @@ def template StoreCondExecute {{ }}; def template AtomicMemOpLoadExecute {{ - Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::%(class_name)sLoad::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -286,7 +286,7 @@ def template AtomicMemOpLoadExecute {{ }}; def template AtomicMemOpStoreExecute {{ - Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::%(class_name)sStore::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -315,7 +315,7 @@ def template AtomicMemOpStoreExecute {{ def template AtomicMemOpEACompExecute {{ Fault - %(class_name)s::%(class_name)s%(op_name)s::eaComp(CPU_EXEC_CONTEXT *xc, + %(class_name)s::%(class_name)s%(op_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -335,7 +335,7 @@ def template AtomicMemOpEACompExecute {{ }}; def template AtomicMemOpLoadInitiateAcc {{ - Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::%(class_name)sLoad::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -355,7 +355,7 @@ def template AtomicMemOpLoadInitiateAcc {{ def template AtomicMemOpStoreInitiateAcc {{ Fault %(class_name)s::%(class_name)sStore::initiateAcc( - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -382,7 +382,7 @@ def template AtomicMemOpStoreInitiateAcc {{ }}; def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -407,7 +407,7 @@ def template StoreCondCompleteAcc {{ def template AtomicMemOpLoadCompleteAcc {{ Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -430,7 +430,7 @@ def template AtomicMemOpLoadCompleteAcc {{ def template AtomicMemOpStoreCompleteAcc {{ Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; } diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa index 4126fcdd4..2d27fd8b5 100644 --- a/src/arch/riscv/isa/formats/basic.isa +++ b/src/arch/riscv/isa/formats/basic.isa @@ -32,7 +32,7 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Basic instruction class declaration template. @@ -63,7 +63,7 @@ def template BasicConstructor {{ // Basic instruction class execute method template. def template BasicExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa index 3de0bb2ff..1f08ca512 100644 --- a/src/arch/riscv/isa/formats/fp.isa +++ b/src/arch/riscv/isa/formats/fp.isa @@ -34,7 +34,7 @@ // Floating point operation instructions // def template FloatExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 9b6bc9eb5..5f469dc8d 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -121,18 +121,18 @@ def template LoadStoreDeclare {{ def template EACompDeclare {{ Fault - eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; + eaComp(ExecContext *, Trace::InstRecord *) const; }}; def template InitiateAccDeclare {{ Fault - initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ Fault - completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template LoadStoreConstructor {{ @@ -146,8 +146,7 @@ def template LoadStoreConstructor {{ def template EACompExecute {{ Fault - %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -201,8 +200,8 @@ def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, def template LoadExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -226,7 +225,7 @@ def template LoadExecute {{ def template LoadInitiateAcc {{ Fault - %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -246,7 +245,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ Fault - %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc, + %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -270,7 +269,7 @@ def template LoadCompleteAcc {{ def template StoreExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -303,7 +302,7 @@ def template StoreExecute {{ def template StoreInitiateAcc {{ Fault - %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -332,7 +331,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ Fault - %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc, + %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 4ef241b2c..70d6ada33 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -201,8 +201,8 @@ def template ImmConstructor {{ def template ImmExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -254,7 +254,7 @@ def template BranchDeclare {{ def template BranchExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -313,8 +313,8 @@ def template JumpDeclare {{ def template JumpExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -446,4 +446,4 @@ def format CSROp(code, *opt_flags) {{ decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) exec_output = BasicExecute.subst(iop) -}};
\ No newline at end of file +}}; diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa index 7a3023a14..aaab21137 100644 --- a/src/arch/riscv/isa/formats/unknown.isa +++ b/src/arch/riscv/isa/formats/unknown.isa @@ -68,7 +68,7 @@ output decoder {{ output exec {{ Fault - Unknown::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = std::make_shared<UnknownInstFault>(); return fault; diff --git a/src/arch/riscv/isa/micro.isa b/src/arch/riscv/isa/micro.isa index bd9102d61..61be076b0 100644 --- a/src/arch/riscv/isa/micro.isa +++ b/src/arch/riscv/isa/micro.isa @@ -30,8 +30,7 @@ // Authors: Alec Roelke def template MacroInitiateAcc {{ - Fault initiateAcc(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const + Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { panic("Tried to execute a macroop directly!\n"); return NoFault; @@ -39,7 +38,7 @@ def template MacroInitiateAcc {{ }}; def template MacroCompleteAcc {{ - Fault completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, + Fault completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { panic("Tried to execute a macroop directly!\n"); @@ -48,7 +47,7 @@ def template MacroCompleteAcc {{ }}; def template MacroExecute {{ - Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("Tried to execute a macroop directly!\n"); return NoFault; diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index 4b61c940c..5d54d0ea9 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -565,7 +565,7 @@ output exec {{ /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled /// if not. Non-full-system mode: always returns NoFault. static inline Fault - checkFpEnableFault(CPU_EXEC_CONTEXT *xc) + checkFpEnableFault(ExecContext *xc) { if (FullSystem) { PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE); @@ -579,7 +579,7 @@ output exec {{ } } static inline Fault - checkVecEnableFault(CPU_EXEC_CONTEXT *xc) + checkVecEnableFault(ExecContext *xc) { return std::make_shared<VecDisabled>(); } diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 7d70e8e60..a81de05ad 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -30,18 +30,18 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; def template DoFpOpDeclare {{ - Fault doFpOp(%(CPU_exec_context)s *, Trace::InstRecord *) + Fault doFpOp(ExecContext *, Trace::InstRecord *) const M5_NO_INLINE; }}; // Definitions of execute methods that panic. def template BasicExecPanic {{ Fault - execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + execute(ExecContext *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); M5_DUMMY_RETURN @@ -113,7 +113,7 @@ def template BasicConstructorWithMnemonic {{ // Basic instruction class execute method template. def template BasicExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -132,7 +132,7 @@ def template BasicExecute {{ def template DoFpOpExecute {{ Fault - %(class_name)s::doFpOp(CPU_EXEC_CONTEXT *xc, + %(class_name)s::doFpOp(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa index eb289931e..b23790738 100644 --- a/src/arch/sparc/isa/formats/branch.isa +++ b/src/arch/sparc/isa/formats/branch.isa @@ -186,7 +186,7 @@ output decoder {{ }}; def template JumpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { // Attempt to execute the instruction @@ -208,7 +208,7 @@ def template JumpExecute {{ def template BranchExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { // Attempt to execute the instruction diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index e60c93cd2..93e5614af 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -237,7 +237,7 @@ output decoder {{ }}; def template IntOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index 34dabc8cb..c35fffd97 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -29,7 +29,7 @@ // This template provides the execute functions for a swap def template SwapExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -68,7 +68,7 @@ def template SwapExecute {{ def template SwapInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -97,7 +97,7 @@ def template SwapInitiateAcc {{ def template SwapCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 00e09ce54..ff14f060f 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -130,7 +130,7 @@ output decoder {{ // This template provides the execute functions for a load def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -158,7 +158,7 @@ def template LoadExecute {{ }}; def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -178,7 +178,7 @@ def template LoadInitiateAcc {{ }}; def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -195,7 +195,7 @@ def template LoadCompleteAcc {{ // This template provides the execute functions for a store def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -226,7 +226,7 @@ def template StoreExecute {{ }}; def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -251,7 +251,7 @@ def template StoreInitiateAcc {{ }}; def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr, CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::completeAcc(PacketPtr, ExecContext * xc, Trace::InstRecord * traceData) const { return NoFault; @@ -260,7 +260,7 @@ def template StoreCompleteAcc {{ def template EACompExecute {{ Fault - %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, + %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -281,17 +281,17 @@ def template EACompExecute {{ }}; def template EACompDeclare {{ - Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; }}; // This delcares the initiateAcc function in memory operations def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; // This declares the completeAcc function in memory operations def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; // Here are some code snippets which check for various fault conditions diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index 2138ba6f5..c57d9346d 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -29,7 +29,7 @@ // This delcares the initiateAcc function in memory operations def template MacroInitiateAcc {{ Fault - initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const + initiateAcc(ExecContext *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; @@ -38,7 +38,7 @@ def template MacroInitiateAcc {{ def template MacroCompleteAcc {{ Fault - completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const + completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; @@ -48,7 +48,7 @@ def template MacroCompleteAcc {{ // This template provides the execute functions for a store def template MacroExecute {{ Fault - execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + execute(ExecContext *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa index aab1f198d..e725f49b0 100644 --- a/src/arch/sparc/isa/formats/nop.isa +++ b/src/arch/sparc/isa/formats/nop.isa @@ -35,7 +35,7 @@ // Per-cpu-model nop execute method. def template NopExec {{ - Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const { // Nothing to see here, move along return NoFault; @@ -79,7 +79,7 @@ output decoder {{ }}; def template NopExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { // Nothing to see here, move along diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 3f6d35330..c581f0fef 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -195,7 +195,7 @@ def template ControlRegConstructor {{ }}; def template PrivExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; diff --git a/src/arch/sparc/isa/formats/trap.isa b/src/arch/sparc/isa/formats/trap.isa index fff30f8ee..8b9ef8c8e 100644 --- a/src/arch/sparc/isa/formats/trap.isa +++ b/src/arch/sparc/isa/formats/trap.isa @@ -72,7 +72,7 @@ output decoder {{ def template TrapExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -85,7 +85,7 @@ def template TrapExecute {{ def template FpUnimplExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/sparc/isa/formats/unimp.isa b/src/arch/sparc/isa/formats/unimp.isa index bd87942ad..f612b8bc6 100644 --- a/src/arch/sparc/isa/formats/unimp.isa +++ b/src/arch/sparc/isa/formats/unimp.isa @@ -109,7 +109,7 @@ output decoder {{ output exec {{ Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " @@ -118,7 +118,7 @@ output exec {{ } Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (!warned) { diff --git a/src/arch/sparc/isa/formats/unknown.isa b/src/arch/sparc/isa/formats/unknown.isa index 2bff7dcf8..226f0191e 100644 --- a/src/arch/sparc/isa/formats/unknown.isa +++ b/src/arch/sparc/isa/formats/unknown.isa @@ -63,7 +63,7 @@ output decoder {{ }}; output exec {{ - Fault Unknown::execute(CPU_EXEC_CONTEXT *xc, + Fault Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return std::make_shared<IllegalInstruction>(); diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa index a4b96c43e..af540962b 100644 --- a/src/arch/x86/isa/formats/basic.isa +++ b/src/arch/x86/isa/formats/basic.isa @@ -40,12 +40,12 @@ // Declarations for execute() methods. def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; }}; // Definitions of execute methods that panic. def template BasicExecPanic {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + Fault execute(ExecContext *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); M5_DUMMY_RETURN @@ -77,7 +77,7 @@ def template BasicConstructor {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa index 265d0f7ef..63ba4cf4e 100644 --- a/src/arch/x86/isa/formats/cpuid.isa +++ b/src/arch/x86/isa/formats/cpuid.isa @@ -68,7 +68,7 @@ output decoder {{ }}; def template CPUIDExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { // If the CPUID instruction used a valid function number, this will diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa index c901ceded..5e68b8738 100644 --- a/src/arch/x86/isa/formats/monitor_mwait.isa +++ b/src/arch/x86/isa/formats/monitor_mwait.isa @@ -47,10 +47,9 @@ def format MonitorInst(code, *opt_flags) {{ // Declarations for execute() methods. def template MwaitExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, - Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template MwaitDeclare {{ @@ -64,7 +63,7 @@ def template MwaitDeclare {{ }}; def template MwaitInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { unsigned s = 0x8; //size @@ -75,7 +74,7 @@ def template MwaitInitiateAcc {{ }}; def template MwaitCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { MicroHalt hltObj(machInst, mnemonic, 0x0); diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa index d33529faa..4d8448b36 100644 --- a/src/arch/x86/isa/formats/nop.isa +++ b/src/arch/x86/isa/formats/nop.isa @@ -72,7 +72,7 @@ output decoder {{ }}; def template NopExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa index 6888af02c..1a47b3ea9 100644 --- a/src/arch/x86/isa/formats/syscall.isa +++ b/src/arch/x86/isa/formats/syscall.isa @@ -74,7 +74,7 @@ output decoder {{ }}; def template SyscallExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa index 7849a4970..ee0600dfd 100644 --- a/src/arch/x86/isa/formats/unimp.isa +++ b/src/arch/x86/isa/formats/unimp.isa @@ -122,7 +122,7 @@ output decoder {{ output exec {{ Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' %s", @@ -131,7 +131,7 @@ output exec {{ } Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, + WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (!warned) { diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa index 585ff1ed5..769ffb7b8 100644 --- a/src/arch/x86/isa/formats/unknown.isa +++ b/src/arch/x86/isa/formats/unknown.isa @@ -74,7 +74,7 @@ output decoder {{ }}; output exec {{ - Fault Unknown::execute(CPU_EXEC_CONTEXT *xc, + Fault Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const { return std::make_shared<InvalidOpcode>(); diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 818cfc3ea..99faa2e03 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -44,7 +44,7 @@ // Execute method for macroops. def template MacroExecPanic {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + Fault execute(ExecContext *, Trace::InstRecord *) const { panic("Tried to execute macroop directly!"); return NoFault; diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index b14202ac5..87e7879f1 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -84,7 +84,7 @@ def template MicroDebugDeclare {{ def template MicroDebugExecute {{ Fault - %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 6ba292977..5973c7d06 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -46,7 +46,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroFpOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 6dd2b6f6b..2f1c267a2 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -48,7 +48,7 @@ // LEA template def template MicroLeaExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -88,7 +88,7 @@ def template MicroLeaDeclare {{ // Load templates def template MicroLoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -118,7 +118,7 @@ def template MicroLoadExecute {{ }}; def template MicroLoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -137,9 +137,8 @@ def template MicroLoadInitiateAcc {{ }}; def template MicroLoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT * xc, - Trace::InstRecord * traceData) const + Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc, + Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -162,7 +161,7 @@ def template MicroLoadCompleteAcc {{ // Store templates def template MicroStoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::execute(ExecContext * xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -190,7 +189,7 @@ def template MicroStoreExecute {{ }}; def template MicroStoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, + Fault %(class_name)s::initiateAcc(ExecContext * xc, Trace::InstRecord * traceData) const { Fault fault = NoFault; @@ -214,7 +213,7 @@ def template MicroStoreInitiateAcc {{ def template MicroStoreCompleteAcc {{ Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const + ExecContext * xc, Trace::InstRecord * traceData) const { %(op_decl)s; %(op_rd)s; @@ -228,12 +227,12 @@ def template MicroStoreCompleteAcc {{ //This delcares the initiateAcc function in memory operations def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; //This declares the completeAcc function in memory operations def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }}; def template MicroLdStOpDeclare {{ diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index c002a1684..ac0438ae0 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -42,7 +42,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroLimmOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 63e22a23f..19bbc6392 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -29,7 +29,7 @@ // Authors: Gabe Black def template MediaOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dc5f0affe..2f8fc4dfc 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -42,7 +42,7 @@ ////////////////////////////////////////////////////////////////////////// def template MicroRegOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -73,7 +73,7 @@ def template MicroRegOpExecute {{ }}; def template MicroRegOpImmExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index 76766e055..601aa6775 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -68,7 +68,7 @@ def template SeqOpDeclare {{ }}; def template SeqOpExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 77c459097..2b1d8ba44 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -88,7 +88,7 @@ def template MicroFaultDeclare {{ }}; def template MicroFaultExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { %(op_decl)s; @@ -104,8 +104,7 @@ def template MicroFaultExecute {{ output exec {{ Fault - MicroHalt::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord * traceData) const + MicroHalt::execute(ExecContext *xc, Trace::InstRecord * traceData) const { xc->tcBase()->suspend(); return NoFault; diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh index 416dfe3c1..00a6e9a33 100644 --- a/src/arch/x86/memhelpers.hh +++ b/src/arch/x86/memhelpers.hh @@ -35,6 +35,7 @@ #include <array> #include "base/types.hh" +#include "cpu/exec_context.hh" #include "sim/byteswap.hh" #include "sim/insttracer.hh" @@ -42,9 +43,8 @@ namespace X86ISA { /// Initiate a read from memory in timing mode. -template <class XC> -Fault -initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, +static Fault +initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, unsigned dataSize, Request::Flags flags) { return xc->initiateMemRead(addr, dataSize, flags); @@ -97,10 +97,9 @@ getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize, } -template <class XC> -Fault -readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem, - unsigned dataSize, Request::Flags flags) +static Fault +readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, + uint64_t &mem, unsigned dataSize, Request::Flags flags) { memset(&mem, 0, sizeof(mem)); Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags); @@ -115,9 +114,9 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem, return fault; } -template <class XC, size_t N> +template <size_t N> Fault -readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, +readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, std::array<uint64_t, N> &mem, unsigned dataSize, unsigned flags) { @@ -139,9 +138,8 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, return fault; } -template <class XC> -Fault -writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem, +static Fault +writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) { @@ -152,9 +150,9 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem, return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res); } -template <class XC, size_t N> +template <size_t N> Fault -writeMemTiming(XC *xc, Trace::InstRecord *traceData, +writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, std::array<uint64_t, N> &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) { @@ -174,9 +172,8 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res); } -template <class XC> -Fault -writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem, +static Fault +writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) { @@ -192,9 +189,9 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem, return fault; } -template <class XC, size_t N> +template <size_t N> Fault -writeMemAtomic(XC *xc, Trace::InstRecord *traceData, +writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, std::array<uint64_t, N> &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) { |