Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem

into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b

6 files changed, 27 insertions, 50 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ec5090eb8..86b8fd2d0 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
         {
             AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
 
-            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
-            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
-            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
-            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
-            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
-            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
-            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
+            retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
+            retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
+            retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
+            retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
+            retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
+            retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
+            retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
         }
         break;
 
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index d289f5785..0c5fe17a7 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/types.hh"
 
-#include <string.h>
+#include <cstring>
 #include <iostream>
 
 class Checkpoint;
@@ -61,7 +61,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(d, sizeof(d)); }
+        { std::memset(d, 0, sizeof(d)); }
     };
 }
 
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 0d65f69e0..dea160992 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/types.hh"
 
 #include <iostream>
-#include <strings.h>
+#include <cstring>
 
 class Checkpoint;
 
@@ -71,7 +71,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(regs, sizeof(regs)); }
+        { std::memset(regs, 0, sizeof(regs)); }
     };
 }
 
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index a350aa05f..773e7d10c 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -192,10 +192,10 @@ output decoder {{
     }
 
     const int AlphaFP::alphaToC99RoundingMode[] = {
-        FE_TOWARDZERO,	// Chopped
-        FE_DOWNWARD,	// Minus_Infinity
-        FE_TONEAREST,	// Normal
-        FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR
+        M5_FE_TOWARDZERO,	// Chopped
+        M5_FE_DOWNWARD,	// Minus_Infinity
+        M5_FE_TONEAREST,	// Normal
+        M5_FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR
     };
 
     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@@ -228,10 +228,10 @@ def template FloatingPointExecute {{
         if (roundingMode == Normal) {
             %(code)s;
         } else {
-            fesetround(getC99RoundingMode(
+            m5_fesetround(getC99RoundingMode(
                            xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
-            fesetround(FE_TONEAREST);
+            m5_fesetround(M5_FE_TONEAREST);
         }
 #else
         if (roundingMode != Normal && !warnedOnRounding) {
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 7665d2d4f..5b0868132 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -109,37 +109,22 @@ def format FpBasic(code, *flags) {{
         fp_code = """
     Fsr |= bits(Fsr,4,0) << 5;
     Fsr = insertBits(Fsr,4,0,0);
-#if defined(__sun) || defined (__OpenBSD__)
-    fp_rnd newrnd = FP_RN;
+    int newrnd = M5_FE_TONEAREST;
     switch (Fsr<31:30>) {
-      case 0: newrnd = FP_RN; break;
-      case 1: newrnd = FP_RZ; break;
-      case 2: newrnd = FP_RP; break;
-      case 3: newrnd = FP_RM; break;
+      case 0: newrnd = M5_FE_TONEAREST; break;
+      case 1: newrnd = M5_FE_TOWARDZERO; break;
+      case 2: newrnd = M5_FE_UPWARD; break;
+      case 3: newrnd = M5_FE_DOWNWARD; break;
     }
-    fp_rnd oldrnd = fpsetround(newrnd);
-#else
-    int newrnd = FE_TONEAREST;
-    switch (Fsr<31:30>) {
-      case 0: newrnd = FE_TONEAREST; break;
-      case 1: newrnd = FE_TOWARDZERO; break;
-      case 2: newrnd = FE_UPWARD; break;
-      case 3: newrnd = FE_DOWNWARD; break;
-    }
-    int oldrnd = fegetround();
-    fesetround(newrnd);
-#endif
+    int oldrnd = m5_fegetround();
+    m5_fesetround(newrnd);
 """
 
         fp_code += code
 
 
         fp_code += """
-#if defined(__sun) || defined (__OpenBSD__)
-    fpsetround(oldrnd);
-#else
-    fesetround(oldrnd);
-#endif
+   m5_fesetround(oldrnd);
 """
         fp_code = filterDoubles(fp_code)
         iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 05e9e8731..e9cd660b5 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -53,22 +53,14 @@ output decoder {{
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
 
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
+#include "base/fenv.hh"
 #include <algorithm>
 
 using namespace SparcISA;
 }};
 
 output exec {{
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
-
-#if defined(__sun) || defined (__OpenBSD__)
-#include <ieeefp.h>
-#endif
+#include "base/fenv.hh"
 
 #if FULL_SYSTEM
 #include "sim/pseudo_inst.hh"