Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

51 files changed, 1110 insertions, 1312 deletions

diff --git a/src/arch/SConscript b/src/arch/SConscript
index a67cf869a..6dfcba185 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -55,7 +55,7 @@ isa_switch_hdrs = Split('''
         mt.hh
         process.hh
         predecoder.hh
-        regfile.hh
+        registers.hh
         remote_gdb.hh
         stacktrace.hh
         tlb.hh
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 2780af104..06f30149d 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -38,7 +38,6 @@ if env['TARGET_ISA'] == 'alpha':
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('regredir.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 8157ef7ec..66c240ef3 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -34,8 +34,6 @@
 
 namespace LittleEndianGuest {}
 
-#include "arch/alpha/ipr.hh"
-#include "arch/alpha/max_inst_regs.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
@@ -45,16 +43,6 @@ class StaticInstPtr;
 namespace AlphaISA {
 
 using namespace LittleEndianGuest;
-using AlphaISAInst::MaxInstSrcRegs;
-using AlphaISAInst::MaxInstDestRegs;
-
-// These enumerate all the registers for dependence tracking.
-enum DependenceTags {
-    // 0..31 are the integer regs 0..31
-    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-    FP_Base_DepTag = 40,
-    Ctrl_Base_DepTag = 72
-};
 
 StaticInstPtr decodeInst(ExtMachInst);
 
@@ -128,21 +116,6 @@ enum mode_type
 // Constants Related to the number of registers
 
 enum {
-    // semantically meaningful register indices
-    ZeroReg = 31,     // architecturally meaningful
-    // the rest of these depend on the ABI
-    StackPointerReg = 30,
-    GlobalPointerReg = 29,
-    ProcedureValueReg = 27,
-    ReturnAddressReg = 26,
-    ReturnValueReg = 0,
-    FramePointerReg = 15,
-
-    SyscallNumReg = 0,
-    FirstArgumentReg = 16,
-    SyscallPseudoReturnReg = 20,
-    SyscallSuccessReg = 19,
-
     LogVMPageSize = 13,       // 8K bytes
     VMPageSize = (1 << LogVMPageSize),
 
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index b231ea855..bcf61db15 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -34,7 +34,7 @@
 
 #include <iosfwd>
 
-#include "arch/alpha/ipr.hh"
+#include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
@@ -45,15 +45,6 @@ class BaseCPU;
 
 namespace AlphaISA {
 
-enum MiscRegIndex
-{
-    MISCREG_FPCR = NumInternalProcRegs,
-    MISCREG_UNIQ,
-    MISCREG_LOCKFLAG,
-    MISCREG_LOCKADDR,
-    MISCREG_INTR
-};
-
 class MiscRegFile
 {
   public:
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
deleted file mode 100644
index 0ddb9da8f..000000000
--- a/src/arch/alpha/regfile.cc
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- *          Kevin Lim
- */
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/regfile.hh"
-#include "arch/alpha/miscregfile.hh"
-#include "cpu/thread_context.hh"
-
-using namespace std;
-
-namespace AlphaISA {
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    // First loop through the integer registers.
-    for (int i = 0; i < NumIntRegs; ++i)
-        dest->setIntReg(i, src->readIntReg(i));
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < NumFloatRegs; ++i)
-        dest->setFloatRegBits(i, src->readFloatRegBits(i));
-
-    // Copy misc. registers
-    copyMiscRegs(src, dest);
-
-    // Lastly copy PC/NPC
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    dest->setMiscRegNoEffect(MISCREG_FPCR,
-        src->readMiscRegNoEffect(MISCREG_FPCR));
-    dest->setMiscRegNoEffect(MISCREG_UNIQ,
-        src->readMiscRegNoEffect(MISCREG_UNIQ));
-    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
-        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
-    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
-        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
-
-    copyIprs(src, dest);
-}
-
-} // namespace AlphaISA
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
deleted file mode 100644
index c5fa981a6..000000000
--- a/src/arch/alpha/regfile.hh
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_REGFILE_HH__
-#define __ARCH_ALPHA_REGFILE_HH__
-
-#include "arch/alpha/ipr.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-    const int NumIntArchRegs = 32;
-    const int NumPALShadowRegs = 8;
-    const int NumFloatArchRegs = 32;
-    // @todo: Figure out what this number really should be.
-    const int NumMiscArchRegs = 77;
-
-    const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-    const int NumFloatRegs = NumFloatArchRegs;
-    const int NumMiscRegs = NumMiscArchRegs;
-
-    const int TotalNumRegs =
-        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_REGFILE_HH__
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
new file mode 100644
index 000000000..ec36ff751
--- /dev/null
+++ b/src/arch/alpha/registers.hh
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_REGISTERS_HH__
+#define __ARCH_ALPHA_REGISTERS_HH__
+
+#include "arch/alpha/ipr.hh"
+#include "arch/alpha/max_inst_regs.hh"
+#include "base/types.hh"
+
+namespace AlphaISA {
+
+using AlphaISAInst::MaxInstSrcRegs;
+using AlphaISAInst::MaxInstDestRegs;
+
+typedef uint8_t RegIndex;
+typedef uint64_t IntReg;
+
+// floating point register file entry type
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
+
+// control register file contents
+typedef uint64_t MiscReg;
+
+union AnyReg
+{
+    IntReg  intreg;
+    FloatReg   fpreg;
+    MiscReg ctrlreg;
+};
+
+enum MiscRegIndex
+{
+    MISCREG_FPCR = NumInternalProcRegs,
+    MISCREG_UNIQ,
+    MISCREG_LOCKFLAG,
+    MISCREG_LOCKADDR,
+    MISCREG_INTR
+};
+
+// semantically meaningful register indices
+const RegIndex ZeroReg = 31;     // architecturally meaningful
+// the rest of these depend on the ABI
+const RegIndex StackPointerReg = 30;
+const RegIndex GlobalPointerReg = 29;
+const RegIndex ProcedureValueReg = 27;
+const RegIndex ReturnAddressReg = 26;
+const RegIndex ReturnValueReg = 0;
+const RegIndex FramePointerReg = 15;
+
+const RegIndex SyscallNumReg = 0;
+const RegIndex FirstArgumentReg = 16;
+const RegIndex SyscallPseudoReturnReg = 20;
+const RegIndex SyscallSuccessReg = 19;
+
+const int NumIntArchRegs = 32;
+const int NumPALShadowRegs = 8;
+const int NumFloatArchRegs = 32;
+// @todo: Figure out what this number really should be.
+const int NumMiscArchRegs = 77;
+
+const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
+const int NumFloatRegs = NumFloatArchRegs;
+const int NumMiscRegs = NumMiscArchRegs;
+
+const int TotalNumRegs =
+    NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
+
+const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+// These enumerate all the registers for dependence tracking.
+enum DependenceTags {
+    // 0..31 are the integer regs 0..31
+    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+    FP_Base_DepTag = 40,
+    Ctrl_Base_DepTag = 72
+};
+
+} // namespace AlphaISA
+
+#endif // __ARCH_ALPHA_REGFILE_HH__
diff --git a/src/arch/alpha/regredir.hh b/src/arch/alpha/regredir.hh
index ac50ec482..6e12be41f 100644
--- a/src/arch/alpha/regredir.hh
+++ b/src/arch/alpha/regredir.hh
@@ -31,7 +31,7 @@
 #ifndef __ARCH_ALPHA_REGREDIR_HH__
 #define __ARCH_ALPHA_REGREDIR_HH__
 
-#include "arch/alpha/regfile.hh"
+#include "arch/alpha/registers.hh"
 
 namespace AlphaISA {
 
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index d670784c4..0d285c3b2 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -38,25 +38,9 @@ namespace AlphaISA {
 
 typedef uint32_t MachInst;
 typedef uint64_t ExtMachInst;
-typedef uint8_t  RegIndex;
 
-typedef uint64_t IntReg;
 typedef uint64_t LargestRead;
 
-// floating point register file entry type
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
-
-// control register file contents
-typedef uint64_t MiscReg;
-
-union AnyReg
-{
-    IntReg  intreg;
-    FloatReg   fpreg;
-    MiscReg ctrlreg;
-};
-
 enum annotes
 {
     ANNOTE_NONE = 0,
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 763da0d4f..c336a4fb3 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -61,5 +61,39 @@ getArgument(ThreadContext *tc, int number, bool fp)
 #endif
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    // First loop through the integer registers.
+    for (int i = 0; i < NumIntRegs; ++i)
+        dest->setIntReg(i, src->readIntReg(i));
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < NumFloatRegs; ++i)
+        dest->setFloatRegBits(i, src->readFloatRegBits(i));
+
+    // Copy misc. registers
+    copyMiscRegs(src, dest);
+
+    // Lastly copy PC/NPC
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    dest->setMiscRegNoEffect(MISCREG_FPCR,
+        src->readMiscRegNoEffect(MISCREG_FPCR));
+    dest->setMiscRegNoEffect(MISCREG_UNIQ,
+        src->readMiscRegNoEffect(MISCREG_UNIQ));
+    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
+        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
+    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
+        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
+
+    copyIprs(src, dest);
+}
+
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 71ee4aceb..de4261418 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -159,6 +159,10 @@ template <class TC>
 void processInterrupts(TC *tc);
 #endif
 
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_UTILITY_HH__
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index ea55314a4..7244252d8 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -41,7 +41,6 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/static_inst.cc')
     Source('isa.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('tlb.cc')
     Source('vtophys.cc')
 
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index d670d673d..542174b6b 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -33,7 +33,6 @@
 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
-#include "arch/arm/max_inst_regs.hh"
 #include "arch/arm/types.hh"
 #include "base/types.hh"
 
@@ -46,8 +45,6 @@ class StaticInstPtr;
 namespace ArmISA
 {
     using namespace LittleEndianGuest;
-    using ArmISAInst::MaxInstSrcRegs;
-    using ArmISAInst::MaxInstDestRegs;
 
     StaticInstPtr decodeInst(ExtMachInst);
 
@@ -98,36 +95,6 @@ namespace ArmISA
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
-    // Constants Related to the number of registers
-    const int NumIntArchRegs = 16;
-    const int NumIntSpecialRegs = 19;
-    const int NumFloatArchRegs = 16;
-    const int NumFloatSpecialRegs = 5;
-    const int NumInternalProcRegs = 0;
-
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-
-    // semantically meaningful register indices
-    const int ReturnValueReg = 0;
-    const int ReturnValueReg1 = 1;
-    const int ReturnValueReg2 = 2;
-    const int ArgumentReg0 = 0;
-    const int ArgumentReg1 = 1;
-    const int ArgumentReg2 = 2;
-    const int ArgumentReg3 = 3;
-    const int FramePointerReg = 11;
-    const int StackPointerReg = 13;
-    const int ReturnAddressReg = 14;
-    const int PCReg = 15;
-
-    const int ZeroReg = NumIntArchRegs;
-    const int AddrReg = ZeroReg + 1; // Used to generate address for uops
-
-    const int SyscallNumReg = ReturnValueReg;
-    const int SyscallPseudoReturnReg = ReturnValueReg;
-    const int SyscallSuccessReg = ReturnValueReg;
-
     const int LogVMPageSize = 12;	// 4K bytes
     const int VMPageSize = (1 << LogVMPageSize);
 
@@ -137,10 +104,6 @@ namespace ArmISA
     const int WordBytes = 4;
     const int HalfwordBytes = 2;
     const int ByteBytes = 1;
-
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 };
 
 using namespace ArmISA;
diff --git a/src/arch/arm/misc_regfile.hh b/src/arch/arm/misc_regfile.hh
index e89826956..6cafc524f 100644
--- a/src/arch/arm/misc_regfile.hh
+++ b/src/arch/arm/misc_regfile.hh
@@ -31,8 +31,7 @@
 #ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 
-#include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/registers.hh"
 #include "arch/arm/types.hh"
 #include "sim/faults.hh"
 
@@ -40,9 +39,8 @@ class ThreadContext;
 
 namespace ArmISA
 {
-    const int NumMiscRegs = NUM_MISCREGS;
-
-    static inline std::string getMiscRegName(RegIndex)
+    static inline std::string
+    getMiscRegName(RegIndex)
     {
         return "";
     }
diff --git a/src/arch/arm/regfile.cc b/src/arch/arm/regfile.cc
deleted file mode 100644
index 6bc694050..000000000
--- a/src/arch/arm/regfile.cc
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#include "arch/arm/regfile.hh"
-#include "base/misc.hh"
-#include "sim/serialize.hh"
-
-using namespace std;
-
-namespace ArmISA
-{
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-MiscRegFile::copyMiscRegs(ThreadContext *tc)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-} // namespace ArmISA
diff --git a/src/arch/arm/regfile.hh b/src/arch/arm/regfile.hh
deleted file mode 100644
index 694351b0f..000000000
--- a/src/arch/arm/regfile.hh
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_REGFILE_HH__
-
-#include "arch/arm/types.hh"
-#include "arch/arm/misc_regfile.hh"
-#include "sim/faults.hh"
-
-class Checkpoint;
-class EventManager;
-class ThreadContext;
-
-namespace ArmISA
-{
-    enum FPControlRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
-    enum FCSRBits {
-        Inexact = 1,
-        Underflow,
-        Overflow,
-        DivideByZero,
-        Invalid,
-        Unimplemented
-    };
-
-    enum FCSRFields {
-        Flag_Field = 1,
-        Enable_Field = 6,
-        Cause_Field = 11
-    };
-
-    enum MiscIntRegNums {
-        zero_reg = NumIntArchRegs,
-        addr_reg,
-
-        rhi,
-        rlo,
-
-        r8_fiq,    /* FIQ mode register bank */
-        r9_fiq,
-        r10_fiq,
-        r11_fiq,
-        r12_fiq,
-
-        r13_fiq,   /* FIQ mode SP and LR */
-        r14_fiq,
-
-        r13_irq,   /* IRQ mode SP and LR */
-        r14_irq,
-
-        r13_svc,   /* SVC mode SP and LR */
-        r14_svc,
-
-        r13_undef, /* UNDEF mode SP and LR */
-        r14_undef,
-
-        r13_abt,   /* ABT mode SP and LR */
-        r14_abt
-    };
-
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace ArmISA
-
-#endif
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
new file mode 100644
index 000000000..7f9b6b828
--- /dev/null
+++ b/src/arch/arm/registers.hh
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_REGISTERS_HH__
+#define __ARCH_ARM_REGISTERS_HH__
+
+#include "arch/arm/max_inst_regs.hh"
+#include "arch/arm/miscregs.hh"
+
+namespace ArmISA {
+
+using ArmISAInst::MaxInstSrcRegs;
+using ArmISAInst::MaxInstDestRegs;
+
+typedef uint8_t  RegIndex;
+
+typedef uint64_t IntReg;
+
+// floating point register file entry type
+typedef uint32_t FloatRegBits;
+typedef float FloatReg;
+
+// cop-0/cop-1 system control register
+typedef uint64_t MiscReg;
+
+// Constants Related to the number of registers
+const int NumIntArchRegs = 16;
+const int NumIntSpecialRegs = 19;
+const int NumFloatArchRegs = 16;
+const int NumFloatSpecialRegs = 5;
+const int NumInternalProcRegs = 0;
+
+const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
+const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+
+const int NumMiscRegs = NUM_MISCREGS;
+
+
+// semantically meaningful register indices
+const int ReturnValueReg = 0;
+const int ReturnValueReg1 = 1;
+const int ReturnValueReg2 = 2;
+const int ArgumentReg0 = 0;
+const int ArgumentReg1 = 1;
+const int ArgumentReg2 = 2;
+const int ArgumentReg3 = 3;
+const int FramePointerReg = 11;
+const int StackPointerReg = 13;
+const int ReturnAddressReg = 14;
+const int PCReg = 15;
+
+const int ZeroReg = NumIntArchRegs;
+const int AddrReg = ZeroReg + 1; // Used to generate address for uops
+
+const int SyscallNumReg = ReturnValueReg;
+const int SyscallPseudoReturnReg = ReturnValueReg;
+const int SyscallSuccessReg = ReturnValueReg;
+
+// These help enumerate all the registers for dependence tracking.
+const int FP_Base_DepTag = NumIntRegs;
+const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+
+typedef union {
+    IntReg   intreg;
+    FloatReg fpreg;
+    MiscReg  ctrlreg;
+} AnyReg;
+
+enum FPControlRegNums {
+   FIR = NumFloatArchRegs,
+   FCCR,
+   FEXR,
+   FENR,
+   FCSR
+};
+
+enum FCSRBits {
+    Inexact = 1,
+    Underflow,
+    Overflow,
+    DivideByZero,
+    Invalid,
+    Unimplemented
+};
+
+enum FCSRFields {
+    Flag_Field = 1,
+    Enable_Field = 6,
+    Cause_Field = 11
+};
+
+enum MiscIntRegNums {
+    zero_reg = NumIntArchRegs,
+    addr_reg,
+
+    rhi,
+    rlo,
+
+    r8_fiq,    /* FIQ mode register bank */
+    r9_fiq,
+    r10_fiq,
+    r11_fiq,
+    r12_fiq,
+
+    r13_fiq,   /* FIQ mode SP and LR */
+    r14_fiq,
+
+    r13_irq,   /* IRQ mode SP and LR */
+    r14_irq,
+
+    r13_svc,   /* SVC mode SP and LR */
+    r14_svc,
+
+    r13_undef, /* UNDEF mode SP and LR */
+    r14_undef,
+
+    r13_abt,   /* ABT mode SP and LR */
+    r14_abt
+};
+
+} // namespace ArmISA
+
+#endif
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 82d1c332c..2c4e1291c 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -113,25 +113,9 @@ namespace ArmISA
         ROR
     };
 
-    typedef uint8_t  RegIndex;
-
-    typedef uint64_t IntReg;
     typedef uint64_t LargestRead;
     // Need to use 64 bits to make sure that read requests get handled properly
 
-    // floating point register file entry type
-    typedef uint32_t FloatRegBits;
-    typedef float FloatReg;
-
-    // cop-0/cop-1 system control register
-    typedef uint64_t MiscReg;
-
-    typedef union {
-        IntReg   intreg;
-        FloatReg fpreg;
-        MiscReg  ctrlreg;
-    } AnyReg;
-
     typedef int RegContextParam;
     typedef int RegContextVal;
 
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 93f207ec7..a2f0ef170 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -113,6 +113,18 @@ namespace ArmISA {
     {
         return NoFault;
     }
+
+    static inline void
+    copyRegs(ThreadContext *src, ThreadContext *dest)
+    {
+        panic("Copy Regs Not Implemented Yet\n");
+    }
+
+    static inline void
+    copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+    {
+        panic("Copy Misc. Regs Not Implemented Yet\n");
+    }
 };
 
 
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 7522dcf0f..a8d5b07b6 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -143,7 +143,6 @@ namespace MipsISA
         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
     };
 
-
     // MIPS modes
     enum mode_type
     {
@@ -154,53 +153,9 @@ namespace MipsISA
         mode_number             // number of modes
     };
 
-  inline mode_type getOperatingMode(MiscReg Stat)
-  {
-    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
-      return mode_kernel;
-    else{
-      if((Stat & 0x18) == 0x8)
-        return mode_supervisor;
-      else if((Stat & 0x18) == 0x10)
-        return mode_user;
-      else return mode_number;
-    }
-  }
-
-
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
-    // Constants Related to the number of registers
-    const int NumIntArchRegs = 32;
-    const int NumIntSpecialRegs = 9;
-    const int NumFloatArchRegs = 32;
-    const int NumFloatSpecialRegs = 5;
-
-    const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-
-    // Static instruction parameters
-    const int MaxInstSrcRegs = 10;
-    const int MaxInstDestRegs = 8;
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;
-    const int AssemblerReg = 1;
-    const int SyscallSuccessReg = 7;
-    const int FirstArgumentReg = 4;
-    const int ReturnValueReg = 2;
-
-    const int KernelReg0 = 26;
-    const int KernelReg1 = 27;
-    const int GlobalPointerReg = 28;
-    const int StackPointerReg = 29;
-    const int FramePointerReg = 30;
-    const int ReturnAddressReg = 31;
-
-    const int SyscallPseudoReturnReg = 3;
-
     const int LogVMPageSize = 13;       // 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);
 
@@ -213,174 +168,6 @@ namespace MipsISA
 
     const int ANNOTE_NONE = 0;
     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
-
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-
-    // Enumerate names for 'Control' Registers in the CPU
-    // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
-    // (Register Number-Register Select) Summary of Register
-    //------------------------------------------------------
-    // The first set of names classify the CP0 names as Register Banks
-    // for easy indexing when using the 'RD + SEL' index combination
-    // in CP0 instructions.
-    enum MiscRegTags {
-        Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
-        MVPControl,
-        MVPConf0,
-        MVPConf1,
-
-        CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
-        VPEControl,
-        VPEConf0,
-        VPEConf1,
-        YQMask,
-        VPESchedule,
-        VPEScheFBack,
-        VPEOpt,
-
-        EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
-        TCStatus,
-        TCBind,
-        TCRestart,
-        TCHalt,
-        TCContext,
-        TCSchedule,
-        TCScheFBack,
-
-        EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
-
-        Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
-        ContextConfig,
-
-        PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
-        PageGrain = Ctrl_Base_DepTag + 41,
-
-        Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
-        SRSConf0,
-        SRSConf1,
-        SRSConf2,
-        SRSConf3,
-        SRSConf4,
-
-        HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
-
-        BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
-
-        Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
-
-        EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
-
-        Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
-
-        Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
-        IntCtl,
-        SRSCtl,
-        SRSMap,
-
-        Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
-
-        EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
-
-        PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
-        EBase,
-
-        Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
-        Config1,
-        Config2,
-        Config3,
-        Config4,
-        Config5,
-        Config6,
-        Config7,
-
-
-        LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
-
-        WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
-        WatchLo1,
-        WatchLo2,
-        WatchLo3,
-        WatchLo4,
-        WatchLo5,
-        WatchLo6,
-        WatchLo7,
-
-        WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
-        WatchHi1,
-        WatchHi2,
-        WatchHi3,
-        WatchHi4,
-        WatchHi5,
-        WatchHi6,
-        WatchHi7,
-
-        XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
-
-                           //Bank 21: 168-175
-
-                           //Bank 22: 176-183
-
-        Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
-        TraceControl1,
-        TraceControl2,
-        UserTraceData,
-        TraceBPC,
-
-        DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
-
-        PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
-        PerfCnt1,
-        PerfCnt2,
-        PerfCnt3,
-        PerfCnt4,
-        PerfCnt5,
-        PerfCnt6,
-        PerfCnt7,
-
-        ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
-
-        CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
-        CacheErr1,
-        CacheErr2,
-        CacheErr3,
-
-        TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
-        DataLo1,
-        TagLo2,
-        DataLo3,
-        TagLo4,
-        DataLo5,
-        TagLo6,
-        DataLo7,
-
-        TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
-        DataHi1,
-        TagHi2,
-        DataHi3,
-        TagHi4,
-        DataHi5,
-        TagHi6,
-        DataHi7,
-
-
-        ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
-
-        DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
-
-        LLFlag = Ctrl_Base_DepTag + 257,
-
-        NumControlRegs
-    };
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-    const int NumMiscRegs = NumControlRegs;
-
-    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-
 };
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 021b8cf73..e202a11aa 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -37,7 +37,7 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "arch/isa_traits.hh"
+#include "arch/registers.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "mem/request.hh"
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 8b4c9f908..b581d5cf0 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -37,9 +37,10 @@
  * ISA-specific helper functions for multithreaded execution.
  */
 
-#include "arch/isa_traits.hh"
 #include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt_constants.hh"
+#include "arch/mips/registers.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "base/misc.hh"
diff --git a/src/arch/mips/regfile.hh b/src/arch/mips/regfile.hh
deleted file mode 100644
index fd32a5af5..000000000
--- a/src/arch/mips/regfile.hh
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __ARCH_MIPS_REGFILE_HH__
-#define __ARCH_MIPS_REGFILE_HH__
-
-#include <iostream>
-#include <string>
-
-#include "arch/mips/isa_traits.hh"
-
-class BaseCPU;
-class Checkpoint;
-class EventManager;
-
-namespace MipsISA
-{
-    const uint32_t MIPS32_QNAN = 0x7fbfffff;
-    const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
-
-    enum FPControlRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
-    enum FCSRBits {
-        Inexact = 1,
-        Underflow,
-        Overflow,
-        DivideByZero,
-        Invalid,
-        Unimplemented
-    };
-
-    enum FCSRFields {
-        Flag_Field = 1,
-        Enable_Field = 6,
-        Cause_Field = 11
-    };
-
-    enum MiscIntRegNums {
-       LO = NumIntArchRegs,
-       HI,
-       DSPACX0,
-       DSPLo1,
-       DSPHi1,
-       DSPACX1,
-       DSPLo2,
-       DSPHi2,
-       DSPACX2,
-       DSPLo3,
-       DSPHi3,
-       DSPACX3,
-       DSPControl,
-       DSPLo0 = LO,
-       DSPHi0 = HI
-    };
-
-    //@TODO: Implementing ShadowSets needs to
-    //edit this value such that:
-    //TotalArchRegs = NumIntArchRegs * ShadowSets
-    const int TotalArchRegs = NumIntArchRegs;
-
-} // namespace MipsISA
-
-#endif
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
new file mode 100644
index 000000000..b996b4717
--- /dev/null
+++ b/src/arch/mips/registers.hh
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#ifndef __ARCH_MIPS_REGISTERS_HH__
+#define __ARCH_MIPS_REGISTERS_HH__
+
+#include "arch/mips/max_inst_regs.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+
+class ThreadContext;
+
+namespace MipsISA
+{
+
+using MipsISAInst::MaxInstSrcRegs;
+using MipsISAInst::MaxInstDestRegs;
+
+// Constants Related to the number of registers
+const int NumIntArchRegs = 32;
+const int NumIntSpecialRegs = 9;
+const int NumFloatArchRegs = 32;
+const int NumFloatSpecialRegs = 5;
+
+const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
+const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
+const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+
+const uint32_t MIPS32_QNAN = 0x7fbfffff;
+const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
+
+enum FPControlRegNums {
+   FIR = NumFloatArchRegs,
+   FCCR,
+   FEXR,
+   FENR,
+   FCSR
+};
+
+enum FCSRBits {
+    Inexact = 1,
+    Underflow,
+    Overflow,
+    DivideByZero,
+    Invalid,
+    Unimplemented
+};
+
+enum FCSRFields {
+    Flag_Field = 1,
+    Enable_Field = 6,
+    Cause_Field = 11
+};
+
+enum MiscIntRegNums {
+   LO = NumIntArchRegs,
+   HI,
+   DSPACX0,
+   DSPLo1,
+   DSPHi1,
+   DSPACX1,
+   DSPLo2,
+   DSPHi2,
+   DSPACX2,
+   DSPLo3,
+   DSPHi3,
+   DSPACX3,
+   DSPControl,
+   DSPLo0 = LO,
+   DSPHi0 = HI
+};
+
+// semantically meaningful register indices
+const int ZeroReg = 0;
+const int AssemblerReg = 1;
+const int SyscallSuccessReg = 7;
+const int FirstArgumentReg = 4;
+const int ReturnValueReg = 2;
+
+const int KernelReg0 = 26;
+const int KernelReg1 = 27;
+const int GlobalPointerReg = 28;
+const int StackPointerReg = 29;
+const int FramePointerReg = 30;
+const int ReturnAddressReg = 31;
+
+const int SyscallPseudoReturnReg = 3;
+
+//@TODO: Implementing ShadowSets needs to
+//edit this value such that:
+//TotalArchRegs = NumIntArchRegs * ShadowSets
+const int TotalArchRegs = NumIntArchRegs;
+
+// These help enumerate all the registers for dependence tracking.
+const int FP_Base_DepTag = NumIntRegs;
+const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+
+// Enumerate names for 'Control' Registers in the CPU
+// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
+// (Register Number-Register Select) Summary of Register
+//------------------------------------------------------
+// The first set of names classify the CP0 names as Register Banks
+// for easy indexing when using the 'RD + SEL' index combination
+// in CP0 instructions.
+enum MiscRegTags {
+    Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
+    MVPControl,
+    MVPConf0,
+    MVPConf1,
+
+    CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
+    VPEControl,
+    VPEConf0,
+    VPEConf1,
+    YQMask,
+    VPESchedule,
+    VPEScheFBack,
+    VPEOpt,
+
+    EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
+    TCStatus,
+    TCBind,
+    TCRestart,
+    TCHalt,
+    TCContext,
+    TCSchedule,
+    TCScheFBack,
+
+    EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
+
+    Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
+    ContextConfig,
+
+    PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
+    PageGrain = Ctrl_Base_DepTag + 41,
+
+    Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
+    SRSConf0,
+    SRSConf1,
+    SRSConf2,
+    SRSConf3,
+    SRSConf4,
+
+    HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
+
+    BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
+
+    Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
+
+    EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
+
+    Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
+
+    Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
+    IntCtl,
+    SRSCtl,
+    SRSMap,
+
+    Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
+
+    EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
+
+    PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
+    EBase,
+
+    Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
+    Config1,
+    Config2,
+    Config3,
+    Config4,
+    Config5,
+    Config6,
+    Config7,
+
+
+    LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
+
+    WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
+    WatchLo1,
+    WatchLo2,
+    WatchLo3,
+    WatchLo4,
+    WatchLo5,
+    WatchLo6,
+    WatchLo7,
+
+    WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
+    WatchHi1,
+    WatchHi2,
+    WatchHi3,
+    WatchHi4,
+    WatchHi5,
+    WatchHi6,
+    WatchHi7,
+
+    XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
+
+                       //Bank 21: 168-175
+
+                       //Bank 22: 176-183
+
+    Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
+    TraceControl1,
+    TraceControl2,
+    UserTraceData,
+    TraceBPC,
+
+    DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
+
+    PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
+    PerfCnt1,
+    PerfCnt2,
+    PerfCnt3,
+    PerfCnt4,
+    PerfCnt5,
+    PerfCnt6,
+    PerfCnt7,
+
+    ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
+
+    CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
+    CacheErr1,
+    CacheErr2,
+    CacheErr3,
+
+    TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
+    DataLo1,
+    TagLo2,
+    DataLo3,
+    TagLo4,
+    DataLo5,
+    TagLo6,
+    DataLo7,
+
+    TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
+    DataHi1,
+    TagHi2,
+    DataHi3,
+    TagHi4,
+    DataHi5,
+    TagHi6,
+    DataHi7,
+
+
+    ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
+
+    DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
+
+    LLFlag = Ctrl_Base_DepTag + 257,
+
+    NumControlRegs
+};
+
+const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+const int NumMiscRegs = NumControlRegs;
+
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
+
+typedef uint16_t  RegIndex;
+
+typedef uint32_t IntReg;
+
+// floating point register file entry type
+typedef uint32_t FloatRegBits;
+typedef float FloatReg;
+
+// cop-0/cop-1 system control register
+typedef uint64_t MiscReg;
+
+typedef union {
+    IntReg   intreg;
+    FloatReg fpreg;
+    MiscReg  ctrlreg;
+} AnyReg;
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 001dc2cb7..18a29122c 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -58,6 +58,21 @@ using namespace MipsISA;
 
 #define MODE2MASK(X)                    (1 << (X))
 
+static inline mode_type
+getOperatingMode(MiscReg Stat)
+{
+    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
+        return mode_kernel;
+    } else if((Stat & 0x18) == 0x8) {
+        return mode_supervisor;
+    } else if((Stat & 0x18) == 0x10) {
+        return mode_user;
+    } else {
+        return mode_number;
+    }
+}
+
+
 TLB::TLB(const Params *p)
     : BaseTLB(p), size(p->size), nlu(0)
 {
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index e38e80975..f203d7d57 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -37,25 +37,9 @@ namespace MipsISA
 {
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
-    typedef uint16_t  RegIndex;
 
-    typedef uint32_t IntReg;
     typedef uint64_t LargestRead;
 
-
-    // floating point register file entry type
-    typedef uint32_t FloatRegBits;
-    typedef float FloatReg;
-
-    // cop-0/cop-1 system control register
-    typedef uint64_t MiscReg;
-
-    typedef union {
-        IntReg   intreg;
-        FloatReg fpreg;
-        MiscReg  ctrlreg;
-    } AnyReg;
-
     //used in FP convert & round function
     enum ConvertType{
         SINGLE_TO_DOUBLE,
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 5908caf68..4723d6301 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -233,18 +233,6 @@ isSnan(void *val_ptr, int size)
     }
 }
 
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
 template <class CPU>
 void
 zeroRegisters(CPU *cpu)
@@ -262,4 +250,16 @@ startupCPU(ThreadContext *tc, int cpuId)
     tc->activate(0/*tc->threadId()*/);
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
 } // namespace MipsISA
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a88c77db9..23c965bd4 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -103,11 +103,6 @@ namespace MipsISA {
         return 0;
     }
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-
     template <class CPU>
     void zeroRegisters(CPU *cpu);
 
@@ -128,6 +123,9 @@ namespace MipsISA {
     // CPU Utility
     //
     void startupCPU(ThreadContext *tc, int cpuId);
+
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 };
 
 
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cfc03b718..5dcadc143 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -37,7 +37,6 @@ if env['TARGET_ISA'] == 'sparc':
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
     Source('utility.cc')
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 135bd58c3..bc9273ad3 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -40,7 +40,7 @@ output header {{
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 #include "base/condcodes.hh"
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 407602f90..2af624d39 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -33,7 +33,6 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "arch/sparc/max_inst_regs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
@@ -48,8 +47,6 @@ namespace SparcISA
 
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
-    using SparcISAInst::MaxInstSrcRegs;
-    using SparcISAInst::MaxInstDestRegs;
 
     // SPARC has a delay slot
     #define ISA_HAS_DELAY_SLOT 1
@@ -57,23 +54,6 @@ namespace SparcISA
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        FP_Base_DepTag = 32*3+9,
-        Ctrl_Base_DepTag = FP_Base_DepTag + 64
-    };
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;      // architecturally meaningful
-    // the rest of these depend on the ABI
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
-    const int StackPointerReg = 14;
-    const int FramePointerReg = 30;
-
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = 9;
-
     //8K. This value is implmentation specific; and should probably
     //be somewhere else.
     const int LogVMPageSize = 13;
diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc
index 28aa1e50c..b39508386 100644
--- a/src/arch/sparc/linux/process.cc
+++ b/src/arch/sparc/linux/process.cc
@@ -32,7 +32,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/linux/process.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 9eff7fcac..c6ba27b93 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -34,6 +34,8 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
 
@@ -43,125 +45,6 @@ class Checkpoint;
 
 namespace SparcISA
 {
-    enum MiscRegIndex
-    {
-        /** Ancillary State Registers */
-//        MISCREG_Y,
-//        MISCREG_CCR,
-        MISCREG_ASI,
-        MISCREG_TICK,
-        MISCREG_FPRS,
-        MISCREG_PCR,
-        MISCREG_PIC,
-        MISCREG_GSR,
-        MISCREG_SOFTINT_SET,
-        MISCREG_SOFTINT_CLR,
-        MISCREG_SOFTINT, /* 10 */
-        MISCREG_TICK_CMPR,
-        MISCREG_STICK,
-        MISCREG_STICK_CMPR,
-
-        /** Privilged Registers */
-        MISCREG_TPC,
-        MISCREG_TNPC,
-        MISCREG_TSTATE,
-        MISCREG_TT,
-        MISCREG_PRIVTICK,
-        MISCREG_TBA,
-        MISCREG_PSTATE, /* 20 */
-        MISCREG_TL,
-        MISCREG_PIL,
-        MISCREG_CWP,
-//        MISCREG_CANSAVE,
-//        MISCREG_CANRESTORE,
-//        MISCREG_CLEANWIN,
-//        MISCREG_OTHERWIN,
-//        MISCREG_WSTATE,
-        MISCREG_GL,
-
-        /** Hyper privileged registers */
-        MISCREG_HPSTATE, /* 30 */
-        MISCREG_HTSTATE,
-        MISCREG_HINTP,
-        MISCREG_HTBA,
-        MISCREG_HVER,
-        MISCREG_STRAND_STS_REG,
-        MISCREG_HSTICK_CMPR,
-
-        /** Floating Point Status Register */
-        MISCREG_FSR,
-
-        /** MMU Internal Registers */
-        MISCREG_MMU_P_CONTEXT,
-        MISCREG_MMU_S_CONTEXT, /* 40 */
-        MISCREG_MMU_PART_ID,
-        MISCREG_MMU_LSU_CTRL,
-
-        /** Scratchpad regiscers **/
-        MISCREG_SCRATCHPAD_R0, /* 60 */
-        MISCREG_SCRATCHPAD_R1,
-        MISCREG_SCRATCHPAD_R2,
-        MISCREG_SCRATCHPAD_R3,
-        MISCREG_SCRATCHPAD_R4,
-        MISCREG_SCRATCHPAD_R5,
-        MISCREG_SCRATCHPAD_R6,
-        MISCREG_SCRATCHPAD_R7,
-
-        /* CPU Queue Registers */
-        MISCREG_QUEUE_CPU_MONDO_HEAD,
-        MISCREG_QUEUE_CPU_MONDO_TAIL,
-        MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
-        MISCREG_QUEUE_DEV_MONDO_TAIL,
-        MISCREG_QUEUE_RES_ERROR_HEAD,
-        MISCREG_QUEUE_RES_ERROR_TAIL,
-        MISCREG_QUEUE_NRES_ERROR_HEAD,
-        MISCREG_QUEUE_NRES_ERROR_TAIL,
-
-        /* All the data for the TLB packed up in one register. */
-        MISCREG_TLB_DATA,
-        MISCREG_NUMMISCREGS
-    };
-
-    struct HPSTATE {
-        const static uint64_t id = 0x800;   // this impl. dependent (id) field m
-        const static uint64_t ibe = 0x400;
-        const static uint64_t red = 0x20;
-        const static uint64_t hpriv = 0x4;
-        const static uint64_t tlz = 0x1;
-    };
-
-
-    struct PSTATE {
-        const static int cle = 0x200;
-        const static int tle = 0x100;
-        const static int mm = 0xC0;
-        const static int pef = 0x10;
-        const static int am = 0x8;
-        const static int priv = 0x4;
-        const static int ie = 0x2;
-    };
-
-    struct STS {
-        const static int st_idle     = 0x00;
-        const static int st_wait     = 0x01;
-        const static int st_halt     = 0x02;
-        const static int st_run      = 0x05;
-        const static int st_spec_run = 0x07;
-        const static int st_spec_rdy = 0x13;
-        const static int st_ready    = 0x19;
-        const static int active      = 0x01;
-        const static int speculative = 0x04;
-        const static int shft_id     = 8;
-        const static int shft_fsm0   = 31;
-        const static int shft_fsm1   = 26;
-        const static int shft_fsm2   = 21;
-        const static int shft_fsm3   = 16;
-    };
-
-
-    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
-    const int NumMiscRegs = MISCREG_NUMMISCREGS;
-
     // The control registers, broken out into fields
     class MiscRegFile
     {
diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh
new file mode 100644
index 000000000..f7fff6ee0
--- /dev/null
+++ b/src/arch/sparc/miscregs.hh
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_MISCREGS_HH__
+#define __ARCH_SPARC_MISCREGS_HH__
+
+#include "base/types.hh"
+
+namespace SparcISA
+{
+    enum MiscRegIndex
+    {
+        /** Ancillary State Registers */
+//        MISCREG_Y,
+//        MISCREG_CCR,
+        MISCREG_ASI,
+        MISCREG_TICK,
+        MISCREG_FPRS,
+        MISCREG_PCR,
+        MISCREG_PIC,
+        MISCREG_GSR,
+        MISCREG_SOFTINT_SET,
+        MISCREG_SOFTINT_CLR,
+        MISCREG_SOFTINT, /* 10 */
+        MISCREG_TICK_CMPR,
+        MISCREG_STICK,
+        MISCREG_STICK_CMPR,
+
+        /** Privilged Registers */
+        MISCREG_TPC,
+        MISCREG_TNPC,
+        MISCREG_TSTATE,
+        MISCREG_TT,
+        MISCREG_PRIVTICK,
+        MISCREG_TBA,
+        MISCREG_PSTATE, /* 20 */
+        MISCREG_TL,
+        MISCREG_PIL,
+        MISCREG_CWP,
+//        MISCREG_CANSAVE,
+//        MISCREG_CANRESTORE,
+//        MISCREG_CLEANWIN,
+//        MISCREG_OTHERWIN,
+//        MISCREG_WSTATE,
+        MISCREG_GL,
+
+        /** Hyper privileged registers */
+        MISCREG_HPSTATE, /* 30 */
+        MISCREG_HTSTATE,
+        MISCREG_HINTP,
+        MISCREG_HTBA,
+        MISCREG_HVER,
+        MISCREG_STRAND_STS_REG,
+        MISCREG_HSTICK_CMPR,
+
+        /** Floating Point Status Register */
+        MISCREG_FSR,
+
+        /** MMU Internal Registers */
+        MISCREG_MMU_P_CONTEXT,
+        MISCREG_MMU_S_CONTEXT, /* 40 */
+        MISCREG_MMU_PART_ID,
+        MISCREG_MMU_LSU_CTRL,
+
+        /** Scratchpad regiscers **/
+        MISCREG_SCRATCHPAD_R0, /* 60 */
+        MISCREG_SCRATCHPAD_R1,
+        MISCREG_SCRATCHPAD_R2,
+        MISCREG_SCRATCHPAD_R3,
+        MISCREG_SCRATCHPAD_R4,
+        MISCREG_SCRATCHPAD_R5,
+        MISCREG_SCRATCHPAD_R6,
+        MISCREG_SCRATCHPAD_R7,
+
+        /* CPU Queue Registers */
+        MISCREG_QUEUE_CPU_MONDO_HEAD,
+        MISCREG_QUEUE_CPU_MONDO_TAIL,
+        MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
+        MISCREG_QUEUE_DEV_MONDO_TAIL,
+        MISCREG_QUEUE_RES_ERROR_HEAD,
+        MISCREG_QUEUE_RES_ERROR_TAIL,
+        MISCREG_QUEUE_NRES_ERROR_HEAD,
+        MISCREG_QUEUE_NRES_ERROR_TAIL,
+
+        /* All the data for the TLB packed up in one register. */
+        MISCREG_TLB_DATA,
+        MISCREG_NUMMISCREGS
+    };
+
+    struct HPSTATE {
+        const static uint64_t id = 0x800;   // this impl. dependent (id) field m
+        const static uint64_t ibe = 0x400;
+        const static uint64_t red = 0x20;
+        const static uint64_t hpriv = 0x4;
+        const static uint64_t tlz = 0x1;
+    };
+
+
+    struct PSTATE {
+        const static int cle = 0x200;
+        const static int tle = 0x100;
+        const static int mm = 0xC0;
+        const static int pef = 0x10;
+        const static int am = 0x8;
+        const static int priv = 0x4;
+        const static int ie = 0x2;
+    };
+
+    struct STS {
+        const static int st_idle     = 0x00;
+        const static int st_wait     = 0x01;
+        const static int st_halt     = 0x02;
+        const static int st_run      = 0x05;
+        const static int st_spec_run = 0x07;
+        const static int st_spec_rdy = 0x13;
+        const static int st_ready    = 0x19;
+        const static int active      = 0x01;
+        const static int speculative = 0x04;
+        const static int shft_id     = 8;
+        const static int shft_fsm0   = 31;
+        const static int shft_fsm1   = 26;
+        const static int shft_fsm2   = 21;
+        const static int shft_fsm3   = 16;
+    };
+
+
+    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
+    const int NumMiscRegs = MISCREG_NUMMISCREGS;
+}
+
+#endif
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
deleted file mode 100644
index 28ffc57aa..000000000
--- a/src/arch/sparc/regfile.cc
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#include "arch/sparc/regfile.hh"
-#include "arch/sparc/miscregfile.hh"
-#include "cpu/thread_context.hh"
-
-using namespace SparcISA;
-
-void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-
-    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
-
-    // Read all the trap level dependent registers and save them off
-    for(int i = 1; i <= MaxTL; i++)
-    {
-        src->setMiscRegNoEffect(MISCREG_TL, i);
-        dest->setMiscRegNoEffect(MISCREG_TL, i);
-
-        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
-        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
-        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
-        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
-    }
-
-    // Save off the traplevel
-    dest->setMiscRegNoEffect(MISCREG_TL, tl);
-    src->setMiscRegNoEffect(MISCREG_TL, tl);
-
-
-    // ASRs
-//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
-//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
-    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
-    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
-    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
-    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
-    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
-    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
-    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
-
-    // Priv Registers
-    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
-    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
-    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
-    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
-    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
-//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
-//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
-//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
-//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
-//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
-    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
-
-    // Hyperprivilged registers
-    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
-    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
-    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
-    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
-            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
-    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
-            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
-
-    // FSR
-    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
-
-    //Strand Status Register
-    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
-            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
-
-    // MMU Registers
-    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
-            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
-    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
-            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
-    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
-            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
-    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
-            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
-
-    // Scratchpad Registers
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
-
-    // Queue Registers
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
-}
-
-void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    //First loop through the integer registers.
-    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
-    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
-    //Globals
-    for (int x = 0; x < MaxGL; ++x) {
-        src->setMiscRegNoEffect(MISCREG_GL, x);
-        dest->setMiscRegNoEffect(MISCREG_GL, x);
-        // Skip %g0 which is always zero.
-        for (int y = 1; y < 8; y++)
-            dest->setIntReg(y, src->readIntReg(y));
-    }
-    //Locals and ins. Outs are all also ins.
-    for (int x = 0; x < NWindows; ++x) {
-         src->setMiscRegNoEffect(MISCREG_CWP, x);
-         dest->setMiscRegNoEffect(MISCREG_CWP, x);
-         for (int y = 16; y < 32; y++)
-             dest->setIntReg(y, src->readIntReg(y));
-    }
-    //Microcode reg and pseudo int regs (misc regs in the integer regfile).
-    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
-        dest->setIntReg(y, src->readIntReg(y));
-
-    //Restore src's GL, CWP
-    src->setMiscRegNoEffect(MISCREG_GL, old_gl);
-    src->setMiscRegNoEffect(MISCREG_CWP, old_cwp);
-
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
-        dest->setFloatRegBits(i, src->readFloatRegBits(i));
-    }
-
-    // Copy misc. registers
-    copyMiscRegs(src, dest);
-
-
-    // Lastly copy PC/NPC
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-    dest->setNextNPC(src->readNextNPC());
-}
-
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/registers.hh
index 28885271f..639b7a487 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/registers.hh
@@ -29,27 +29,51 @@
  *          Ali Saidi
  */
 
-#ifndef __ARCH_SPARC_REGFILE_HH__
-#define __ARCH_SPARC_REGFILE_HH__
+#ifndef __ARCH_SPARC_REGISTERS_HH__
+#define __ARCH_SPARC_REGISTERS_HH__
 
-#include <iostream>
-#include <string>
-
-#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/max_inst_regs.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
-
-class Checkpoint;
-class EventManager;
-class ThreadContext;
+#include "base/types.hh"
 
 namespace SparcISA
 {
-    const int NumIntArchRegs = 32;
-    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+    using SparcISAInst::MaxInstSrcRegs;
+    using SparcISAInst::MaxInstDestRegs;
+
+    typedef uint64_t IntReg;
+    typedef uint64_t MiscReg;
+    typedef float FloatReg;
+    typedef uint32_t FloatRegBits;
+    typedef union
+    {
+        IntReg intReg;
+        FloatReg fpreg;
+        MiscReg ctrlreg;
+    } AnyReg;
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+    typedef uint16_t RegIndex;
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+    // These enumerate all the registers for dependence tracking.
+    enum DependenceTags {
+        FP_Base_DepTag = 32*3+9,
+        Ctrl_Base_DepTag = FP_Base_DepTag + 64
+    };
+
+    // semantically meaningful register indices
+    const int ZeroReg = 0;      // architecturally meaningful
+    // the rest of these depend on the ABI
+    const int ReturnAddressReg = 31; // post call, precall is 15
+    const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
+    const int StackPointerReg = 14;
+    const int FramePointerReg = 30;
+
+    // Some OS syscall use a second register (o1) to return a second value
+    const int SyscallPseudoReturnReg = 9;
+
+    const int NumIntArchRegs = 32;
+    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
 
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc
index 22924736b..eafb488df 100644
--- a/src/arch/sparc/solaris/process.cc
+++ b/src/arch/sparc/solaris/process.cc
@@ -30,7 +30,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/solaris/process.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index c7ece9dfa..70558ec6d 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -39,19 +39,7 @@ namespace SparcISA
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
 
-    typedef uint64_t IntReg;
     typedef Twin64_t LargestRead;
-    typedef uint64_t MiscReg;
-    typedef float FloatReg;
-    typedef uint32_t FloatRegBits;
-    typedef union
-    {
-        IntReg intReg;
-        FloatReg fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
-
-    typedef uint16_t RegIndex;
 
     struct CoreSpecific {
         int core_type;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index d4cc286e6..9c9b833fe 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -61,4 +61,159 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
     M5_DUMMY_RETURN
 #endif
 }
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+
+    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
+
+    // Read all the trap level dependent registers and save them off
+    for(int i = 1; i <= MaxTL; i++)
+    {
+        src->setMiscRegNoEffect(MISCREG_TL, i);
+        dest->setMiscRegNoEffect(MISCREG_TL, i);
+
+        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
+        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
+        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
+        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
+    }
+
+    // Save off the traplevel
+    dest->setMiscRegNoEffect(MISCREG_TL, tl);
+    src->setMiscRegNoEffect(MISCREG_TL, tl);
+
+
+    // ASRs
+//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
+//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
+    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
+    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
+    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
+    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
+
+    // Priv Registers
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
+    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
+    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
+    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
+//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
+//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
+//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
+//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
+//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
+    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
+
+    // Hyperprivilged registers
+    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
+    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
+    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
+            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
+
+    // FSR
+    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
+
+    //Strand Status Register
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+
+    // MMU Registers
+    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
+            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
+    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
+            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
+
+    // Scratchpad Registers
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
+
+    // Queue Registers
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
+}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    //First loop through the integer registers.
+    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
+    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
+    //Globals
+    for (int x = 0; x < MaxGL; ++x) {
+        src->setMiscRegNoEffect(MISCREG_GL, x);
+        dest->setMiscRegNoEffect(MISCREG_GL, x);
+        // Skip %g0 which is always zero.
+        for (int y = 1; y < 8; y++)
+            dest->setIntReg(y, src->readIntReg(y));
+    }
+    //Locals and ins. Outs are all also ins.
+    for (int x = 0; x < NWindows; ++x) {
+         src->setMiscRegNoEffect(MISCREG_CWP, x);
+         dest->setMiscRegNoEffect(MISCREG_CWP, x);
+         for (int y = 16; y < 32; y++)
+             dest->setIntReg(y, src->readIntReg(y));
+    }
+    //Microcode reg and pseudo int regs (misc regs in the integer regfile).
+    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
+        dest->setIntReg(y, src->readIntReg(y));
+
+    //Restore src's GL, CWP
+    src->setMiscRegNoEffect(MISCREG_GL, old_gl);
+    src->setMiscRegNoEffect(MISCREG_CWP, old_cwp);
+
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
+        dest->setFloatRegBits(i, src->readFloatRegBits(i));
+    }
+
+    // Copy misc. registers
+    copyMiscRegs(src, dest);
+
+
+    // Lastly copy PC/NPC
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+    dest->setNextNPC(src->readNextNPC());
+}
 } //namespace SPARC_ISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index c0c3756f5..551570723 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -116,6 +116,10 @@ namespace SparcISA
 #endif
     }
 
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace SparcISA
 
 #endif
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index f500089f3..1cb0edaf2 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -99,7 +99,6 @@ if env['TARGET_ISA'] == 'x86':
     Source('pagetable.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
-    Source('regfile.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
     Source('utility.cc')
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index cdb1bf863..bcefd4456 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -60,6 +60,7 @@
 
 #include "arch/x86/intregs.hh"
 #include "arch/x86/segmentregs.hh"
+#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 
 namespace X86ISA
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 8626f117a..93685cd9f 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -103,7 +103,7 @@ output header {{
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/isa_traits.hh"
-#include "arch/x86/regfile.hh"
+#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 2b549bb4a..9f1b7b7c4 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -58,8 +58,6 @@
 #ifndef __ARCH_X86_ISATRAITS_HH__
 #define __ARCH_X86_ISATRAITS_HH__
 
-#include "arch/x86/intregs.hh"
-#include "arch/x86/max_inst_regs.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/types.hh"
@@ -73,8 +71,6 @@ namespace X86ISA
     //This makes sure the little endian version of certain functions
     //are used.
     using namespace LittleEndianGuest;
-    using X86ISAInst::MaxInstSrcRegs;
-    using X86ISAInst::MaxInstDestRegs;
 
     // X86 does not have a delay slot
 #define ISA_HAS_DELAY_SLOT 0
@@ -83,36 +79,6 @@ namespace X86ISA
     //XXX This needs to be set to an intermediate instruction struct
     //which encodes this instruction
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        //There are 16 microcode registers at the moment. This is an
-        //unusually large constant to make sure there isn't overflow.
-        FP_Base_DepTag = 128,
-        Ctrl_Base_DepTag =
-            FP_Base_DepTag +
-            //mmx/x87 registers
-            8 +
-            //xmm registers
-            16 * 2 +
-            //The microcode fp registers
-            8 +
-            //The indices that are mapped over the fp stack
-            8
-    };
-
-    // semantically meaningful register indices
-    //There is no such register in X86
-    const int ZeroReg = NUM_INTREGS;
-    const int StackPointerReg = INTREG_RSP;
-    //X86 doesn't seem to have a link register
-    const int ReturnAddressReg = 0;
-    const int ReturnValueReg = INTREG_RAX;
-    const int FramePointerReg = INTREG_RBP;
-
-    // Some OS syscalls use a second register (rdx) to return a second
-    // value
-    const int SyscallPseudoReturnReg = INTREG_RDX;
-
     //4k. This value is not constant on x86.
     const int LogVMPageSize = 12;
     const int VMPageSize = (1 << LogVMPageSize);
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 1d109ae27..b7d72d594 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -57,7 +57,7 @@
 
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/linux/process.hh"
-#include "arch/x86/regfile.hh"
+#include "arch/x86/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index f2329b7b4..8e8adc63b 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -92,7 +92,7 @@
 
 #include "arch/x86/faults.hh"
 #include "arch/x86/miscregs.hh"
-#include "arch/x86/types.hh"
+#include "arch/x86/registers.hh"
 #include "base/types.hh"
 
 class Checkpoint;
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
deleted file mode 100644
index 67ef0b128..000000000
--- a/src/arch/x86/regfile.cc
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
- *
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use.  Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- *     Director of Intellectual Property Licensing
- *     Office of Strategy and Technology
- *     Hewlett-Packard Company
- *     1501 Page Mill Road
- *     Palo Alto, California  94304
- *
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.  Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.  Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.  No right of
- * sublicense is granted herewith.  Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses.  Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/x86/miscregs.hh"
-#include "arch/x86/regfile.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-
-void
-X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    warn("copyMiscRegs is naively implemented for x86\n");
-    for (int i = 0; i < NUM_MISCREGS; ++i) {
-        if ( ( i != MISCREG_CR1 &&
-             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
-             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
-             continue;
-        }
-        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-    }
-}
-
-void
-X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("copyRegs not implemented for x86!\n");
-    //copy int regs
-    //copy float regs
-    copyMiscRegs(src, dest);
-
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/registers.hh
index fd9d6d546..e221c4a81 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/registers.hh
@@ -55,40 +55,78 @@
  * Authors: Gabe Black
  */
 
-#ifndef __ARCH_X86_REGFILE_HH__
-#define __ARCH_X86_REGFILE_HH__
-
-#include <iostream>
-#include <string>
+#ifndef __ARCH_X86_REGISTERS_HH__
+#define __ARCH_X86_REGISTERS_HH__
 
 #include "arch/x86/intregs.hh"
+#include "arch/x86/max_inst_regs.hh"
 #include "arch/x86/miscregs.hh"
 #include "arch/x86/x86_traits.hh"
 
-class Checkpoint;
-class EventManager;
-class ThreadContext;
-
 namespace X86ISA
 {
-    const int NumMiscArchRegs = NUM_MISCREGS;
-    const int NumMiscRegs = NUM_MISCREGS;
+using X86ISAInst::MaxInstSrcRegs;
+using X86ISAInst::MaxInstDestRegs;
+const int NumMiscArchRegs = NUM_MISCREGS;
+const int NumMiscRegs = NUM_MISCREGS;
+
+const int NumIntArchRegs = NUM_INTREGS;
+const int NumIntRegs =
+    NumIntArchRegs + NumMicroIntRegs +
+    NumPseudoIntRegs + NumImplicitIntRegs;
 
-    const int NumIntArchRegs = NUM_INTREGS;
-    const int NumIntRegs =
-        NumIntArchRegs + NumMicroIntRegs +
-        NumPseudoIntRegs + NumImplicitIntRegs;
+//Each 128 bit xmm register is broken into two effective 64 bit registers.
+const int NumFloatRegs =
+    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
+const int NumFloatArchRegs = NumFloatRegs + 8;
 
-    //Each 128 bit xmm register is broken into two effective 64 bit registers.
-    const int NumFloatRegs =
-        NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
-    const int NumFloatArchRegs = NumFloatRegs + 8;
+// These enumerate all the registers for dependence tracking.
+enum DependenceTags {
+    //There are 16 microcode registers at the moment. This is an
+    //unusually large constant to make sure there isn't overflow.
+    FP_Base_DepTag = 128,
+    Ctrl_Base_DepTag =
+        FP_Base_DepTag +
+        //mmx/x87 registers
+        8 +
+        //xmm registers
+        16 * 2 +
+        //The microcode fp registers
+        8 +
+        //The indices that are mapped over the fp stack
+        8
+};
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+// semantically meaningful register indices
+//There is no such register in X86
+const int ZeroReg = NUM_INTREGS;
+const int StackPointerReg = INTREG_RSP;
+//X86 doesn't seem to have a link register
+const int ReturnAddressReg = 0;
+const int ReturnValueReg = INTREG_RAX;
+const int FramePointerReg = INTREG_RBP;
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+// Some OS syscalls use a second register (rdx) to return a second
+// value
+const int SyscallPseudoReturnReg = INTREG_RDX;
+
+typedef uint64_t IntReg;
+//XXX Should this be a 128 bit structure for XMM memory ops?
+typedef uint64_t LargestRead;
+typedef uint64_t MiscReg;
+
+//These floating point types are correct for mmx, but not
+//technically for x87 (80 bits) or at all for xmm (128 bits)
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
+typedef union
+{
+    IntReg intReg;
+    FloatReg fpReg;
+    MiscReg ctrlReg;
+} AnyReg;
 
-    int InterruptLevel(uint64_t softint);
+typedef uint16_t RegIndex;
 
 }; // namespace X86ISA
 
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index c06d664eb..bdf3a814e 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -230,24 +230,6 @@ namespace X86ISA
         return true;
     }
 
-    typedef uint64_t IntReg;
-    //XXX Should this be a 128 bit structure for XMM memory ops?
-    typedef uint64_t LargestRead;
-    typedef uint64_t MiscReg;
-
-    //These floating point types are correct for mmx, but not
-    //technically for x87 (80 bits) or at all for xmm (128 bits)
-    typedef double FloatReg;
-    typedef uint64_t FloatRegBits;
-    typedef union
-    {
-        IntReg intReg;
-        FloatReg fpReg;
-        MiscReg ctrlReg;
-    } AnyReg;
-
-    typedef uint16_t RegIndex;
-
     struct CoreSpecific {
         int core_type;
     };
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 9e96b654d..802328db1 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -225,4 +225,30 @@ void startupCPU(ThreadContext *tc, int cpuId)
 #endif
 }
 
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    warn("copyMiscRegs is naively implemented for x86\n");
+    for (int i = 0; i < NUM_MISCREGS; ++i) {
+        if ( ( i != MISCREG_CR1 &&
+             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
+             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
+             continue;
+        }
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+    }
+}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("copyRegs not implemented for x86!\n");
+    //copy int regs
+    //copy float regs
+    copyMiscRegs(src, dest);
+
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+}
+
 } //namespace X86_ISA
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index dbb2bc361..d305e2599 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -154,6 +154,10 @@ namespace X86ISA
 #endif
 
     void startupCPU(ThreadContext *tc, int cpuId);
+
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 };
 
 #endif // __ARCH_X86_UTILITY_HH__