x86: implement x87 fp instruction fnstsw

This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.

5 files changed, 44 insertions, 5 deletions

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 0b5523864..5305b1058 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -127,6 +127,13 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
     if (miscReg == MISCREG_TSC) {
         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
     }
+
+    if (miscReg == MISCREG_FSW) {
+        MiscReg fsw = regVal[MISCREG_FSW];
+        MiscReg top = regVal[MISCREG_X87_TOP];
+        return (fsw & (~(7ULL << 11))) + (top << 11);
+    }
+
     return readMiscRegNoEffect(miscReg);
 }
 
diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa
index 4ed902192..3af68cd54 100644
--- a/src/arch/x86/isa/decoder/x87.isa
+++ b/src/arch/x86/isa/decoder/x87.isa
@@ -112,7 +112,7 @@ format WarnUnimpl {
                     0x6: fsin();
                     0x7: fcos();
                 }
-                default: fnstcw_Mw();
+                default: Inst::FNSTCW(Mw);
             }
         }
         //0x2: esc2();
@@ -247,7 +247,7 @@ format WarnUnimpl {
             }
             0x7: decode MODRM_MOD {
                 0x3: Inst::UD2();
-                default: fnstsw();
+                default: Inst::FNSTSW(Mw);
             }
         }
         //0x6: esc6();
@@ -310,7 +310,7 @@ format WarnUnimpl {
             }
             0x4: decode MODRM_MOD {
                 0x3: decode MODRM_RM {
-                    0x0: fnstsw();
+                    0x0: Inst::FNSTSW(rAw);
                     default: Inst::UD2();
                 }
                 default: fbld();
diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
index 0fc4ef7b7..5657c8d47 100644
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
@@ -38,5 +38,15 @@
 microcode = '''
 # FLDCW
 # FSTCW
-# FNSTCW
+
+def macroop FNSTCW_M {
+    rdval t1, fcw
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTCW_P {
+    rdip t7
+    rdval t1, fcw
+    st t1, seg, sib, disp, dataSize=2
+};
 '''
diff --git a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
index 2739852a4..65ff8006b 100644
--- a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
+++ b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
@@ -36,6 +36,22 @@
 # Authors: Gabe Black
 
 microcode = '''
+
 # FSTSW
-# FNSTSW
+
+def macroop FNSTSW_R {
+    rdval t1, fsw
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop FNSTSW_M {
+    rdval t1, fsw
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTSW_P {
+    rdip t7
+    rdval t1, fsw
+    st t1, seg, riprel, disp, dataSize=2
+};
 '''
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 10404ec7a..b1fdfb54c 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -207,6 +207,12 @@ let {{
     assembler.symbols["sti"] = stack_index("env.reg")
     assembler.symbols["stim"] = stack_index("env.regm")
 
+    def readFpReg(reg_name):
+        return regIdx("MISCREG_%s" % reg_name)
+
+    assembler.symbols["fsw"] = readFpReg("FSW")
+    assembler.symbols["fcw"] = readFpReg("FCW")
+
     macroopDict = assembler.assemble(microcode)
 
     decoder_output += mainRom.getDefinition()