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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:18 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:18 -0500
commit0abec5356427798568cc0008add4a4038443c548 (patch)
tree51f6a584133a04c0179940a7c2802cc4e4fa0f4f /src/arch
parent9223725973d5c5b7082bae2550f3c2111fbb3501 (diff)
downloadgem5-0abec5356427798568cc0008add4a4038443c548.tar.xz
ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/insts/mem.cc36
-rw-r--r--src/arch/arm/insts/mem.hh36
2 files changed, 37 insertions, 35 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index ccac3a25d..3dde0aa35 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -48,6 +48,42 @@ using namespace std;
namespace ArmISA
{
+void
+MemoryReg::printOffset(std::ostream &os) const
+{
+ if (!add)
+ os << "-";
+ printReg(os, index);
+ if (shiftType != LSL || shiftAmt != 0) {
+ switch (shiftType) {
+ case LSL:
+ ccprintf(os, " LSL #%d", shiftAmt);
+ break;
+ case LSR:
+ if (shiftAmt == 0) {
+ ccprintf(os, " LSR #%d", 32);
+ } else {
+ ccprintf(os, " LSR #%d", shiftAmt);
+ }
+ break;
+ case ASR:
+ if (shiftAmt == 0) {
+ ccprintf(os, " ASR #%d", 32);
+ } else {
+ ccprintf(os, " ASR #%d", shiftAmt);
+ }
+ break;
+ case ROR:
+ if (shiftAmt == 0) {
+ ccprintf(os, " RRX");
+ } else {
+ ccprintf(os, " ROR #%d", shiftAmt);
+ }
+ break;
+ }
+ }
+}
+
string
Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index 50f718b99..609afa9aa 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -246,41 +246,7 @@ class MemoryReg : public Memory
shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
{}
- void
- printOffset(std::ostream &os) const
- {
- if (!add)
- os << "-";
- printReg(os, index);
- if (shiftType != LSL || shiftAmt != 0) {
- switch (shiftType) {
- case LSL:
- ccprintf(os, " LSL #%d", shiftAmt);
- break;
- case LSR:
- if (shiftAmt == 0) {
- ccprintf(os, " LSR #%d", 32);
- } else {
- ccprintf(os, " LSR #%d", shiftAmt);
- }
- break;
- case ASR:
- if (shiftAmt == 0) {
- ccprintf(os, " ASR #%d", 32);
- } else {
- ccprintf(os, " ASR #%d", shiftAmt);
- }
- break;
- case ROR:
- if (shiftAmt == 0) {
- ccprintf(os, " RRX");
- } else {
- ccprintf(os, " ROR #%d", shiftAmt);
- }
- break;
- }
- }
- }
+ void printOffset(std::ostream &os) const;
};
class MemoryDReg : public MemoryReg