cpu, arch: fix the type used for the request flags

Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

5 files changed, 19 insertions, 16 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index fabbe0756..2ae0bd7dc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1465,7 +1465,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_ATS1HR:
           case MISCREG_ATS1HW:
             {
-              unsigned flags = 0;
+              Request::Flags flags = 0;
               BaseTLB::Mode mode = BaseTLB::Read;
               TLB::ArmTranslationType tranType = TLB::NormalTran;
               Fault fault;
@@ -1710,7 +1710,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_AT_S1E3W_Xt:
             {
                 RequestPtr req = new Request;
-                unsigned flags = 0;
+                Request::Flags flags = 0;
                 BaseTLB::Mode mode = BaseTLB::Read;
                 TLB::ArmTranslationType tranType = TLB::NormalTran;
                 Fault fault;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a19a609b7..6658657aa 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -64,6 +64,7 @@
 #include "debug/TLB.hh"
 #include "debug/TLBVerbose.hh"
 #include "mem/page_table.hh"
+#include "mem/request.hh"
 #include "params/ArmTLB.hh"
 #include "sim/full_system.hh"
 #include "sim/process.hh"
@@ -555,7 +556,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
     else
         vaddr = vaddr_tainted;
-    uint32_t flags = req->getFlags();
+    Request::Flags flags = req->getFlags();
 
     bool is_fetch = (mode == Execute);
     bool is_write = (mode == Write);
@@ -588,7 +589,7 @@ Fault
 TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
 {
     Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
-    uint32_t flags = req->getFlags();
+    Request::Flags flags = req->getFlags();
     bool is_fetch  = (mode == Execute);
     bool is_write  = (mode == Write);
     bool is_priv   = isPriv && !(flags & UserMode);
@@ -760,7 +761,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
     Addr vaddr_tainted = req->getVaddr();
     Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
 
-    uint32_t flags = req->getFlags();
+    Request::Flags flags = req->getFlags();
     bool is_fetch  = (mode == Execute);
     bool is_write  = (mode == Write);
     bool is_priv M5_VAR_USED  = isPriv && !(flags & UserMode);
@@ -967,7 +968,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
     else
         vaddr = vaddr_tainted;
-    uint32_t flags = req->getFlags();
+    Request::Flags flags = req->getFlags();
 
     bool is_fetch  = (mode == Execute);
     bool is_write  = (mode == Write);
@@ -981,7 +982,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
             isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
 
     DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
-                 "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
+                 "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2,
                  scr, sctlr, flags, tranType);
 
     if ((req->isInstFetch() && (!sctlr.i)) ||
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index b12e7b0b1..f1c1d3322 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -54,7 +54,7 @@
 template <class XC, class MemT>
 Fault
 initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
-                MemT &mem, unsigned flags)
+                MemT &mem, Request::Flags flags)
 {
     return xc->initiateMemRead(addr, sizeof(MemT), flags);
 }
@@ -73,7 +73,7 @@ getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 template <class XC, class MemT>
 Fault
 readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
-        unsigned flags)
+              Request::Flags flags)
 {
     memset(&mem, 0, sizeof(mem));
     Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
@@ -89,7 +89,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
 template <class XC, class MemT>
 Fault
 writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
-        unsigned flags, uint64_t *res)
+               Request::Flags flags, uint64_t *res)
 {
     if (traceData) {
         traceData->setData(mem);
@@ -102,7 +102,7 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
 template <class XC, class MemT>
 Fault
 writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
-        Addr addr, unsigned flags, uint64_t *res)
+               Addr addr, Request::Flags flags, uint64_t *res)
 {
     if (traceData) {
         traceData->setData(mem);
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index b13207ec4..416dfe3c1 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -45,7 +45,7 @@ namespace X86ISA
 template <class XC>
 Fault
 initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
-                unsigned dataSize, unsigned flags)
+                unsigned dataSize, Request::Flags flags)
 {
     return xc->initiateMemRead(addr, dataSize, flags);
 }
@@ -100,7 +100,7 @@ getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize,
 template <class XC>
 Fault
 readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
-        unsigned dataSize, unsigned flags)
+              unsigned dataSize, Request::Flags flags)
 {
     memset(&mem, 0, sizeof(mem));
     Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
@@ -142,7 +142,8 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr,
 template <class XC>
 Fault
 writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
-        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+               unsigned dataSize, Addr addr, Request::Flags flags,
+               uint64_t *res)
 {
     if (traceData) {
         traceData->setData(mem);
@@ -176,7 +177,8 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData,
 template <class XC>
 Fault
 writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
-        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+               unsigned dataSize, Addr addr, Request::Flags flags,
+               uint64_t *res)
 {
     if (traceData) {
         traceData->setData(mem);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index d0e77bc9b..be43cb06e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -273,7 +273,7 @@ Fault
 TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
         Mode mode, bool &delayedResponse, bool timing)
 {
-    uint32_t flags = req->getFlags();
+    Request::Flags flags = req->getFlags();
     int seg = flags & SegmentFlagMask;
     bool storeCheck = flags & (StoreCheck << FlagShift);