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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
| commit | e681c0f7b30f521805ebec04271435306f4c56ed (patch) | |
| tree | 4b060d7175b0d90c9d4a731d0cad304b60dac029 /src/arch | |
| parent | 719f9a6d4fba16af38dcfd62b25a4d708156699f (diff) | |
| download | gem5-e681c0f7b30f521805ebec04271435306f4c56ed.tar.xz | |
O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e0a34a1b1..b62b8400d 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -490,7 +490,8 @@ decode OP default Unknown::unknown() 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); // 0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); + 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, + IsSquashAfter); // 0x04-0x05 should cause an illegal instruction exception 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); // 0x07-0x0E should cause an illegal instruction exception |