Started adding a system to output data after every instruction.

src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
    Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
    Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
    Options to turn on output after every instruction. They are commented out.

--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0

4 files changed, 30 insertions, 0 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index c31619408..43b48a0ab 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -45,6 +45,21 @@ class ThreadContext;
 namespace AlphaISA
 {
 
+    static inline std::string getIntRegName(RegIndex)
+    {
+        return "";
+    }
+
+    static inline std::string getFloatRegName(RegIndex)
+    {
+        return "";
+    }
+
+    static inline std::string getMiscRegName(RegIndex)
+    {
+        return "";
+    }
+
     class IntRegFile
     {
       protected:
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index f057461ae..e9447d39e 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -41,6 +41,11 @@ class Checkpoint;
 
 namespace MipsISA
 {
+    static inline std::string getFloatRegName(RegIndex)
+    {
+        return "";
+    }
+
     const uint32_t MIPS32_QNAN = 0x7fbfffff;
     const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
 
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 5496fc1f5..a45a17a85 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -41,6 +41,11 @@ class ThreadContext;
 
 namespace MipsISA
 {
+    static inline std::string getIntRegName(RegIndex)
+    {
+        return "";
+    }
+
     enum MiscIntRegNums {
        HI = NumIntArchRegs,
        LO
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 66d3218d4..c2e1c3176 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -39,6 +39,11 @@ class ThreadContext;
 
 namespace MipsISA
 {
+    static inline std::string getMiscRegName(RegIndex)
+    {
+        return "";
+    }
+
     //Coprocessor 0 Register Names
     enum MiscRegTags {
         //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8