scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

12 files changed, 65 insertions, 3 deletions

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 3865cffe2..00a37d17b 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -81,7 +81,7 @@ def format ArmMsrMrs() {{
 let {{
     header_output = '''
     StaticInstPtr
-    decodeMcrMrc15(ExtMachInst machInst);
+    decodeMcrMrc14(ExtMachInst machInst);
     '''
     decoder_output = '''
     StaticInstPtr
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index a32bf6dfc..272f16b17 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -38,7 +38,9 @@
 
 
 let {{
-    header_output = ""
+    header_output = '''
+    uint64_t join32to64(uint32_t r1, uint32_t r0);
+    '''
     decoder_output = '''
     uint64_t join32to64(uint32_t r1, uint32_t r0)
     {
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index d8e5eb111..1480a5589 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -172,6 +172,13 @@ output decoder {{
 
 }};
 
+output header {{
+        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
+
+        bool isMMUTLB(%(CPU_exec_context)s *xc);
+
+}};
+
 output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index b288b7b20..9dfae3f44 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -135,6 +135,12 @@ def template DspHiLoExecute {{
         }
 }};
 
+output header {{
+    bool isDspEnabled(%(CPU_exec_context)s *xc);
+
+    bool isDspPresent(%(CPU_exec_context)s *xc);
+}};
+
 //Outputs to decoder.cc
 output decoder {{
 }};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 63823f404..e6f0258a0 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -86,6 +86,11 @@ output decoder {{
         }
 }};
 
+output header {{
+        void fpResetCauseBits(%(CPU_exec_context)s *cpu);
+
+}};
+
 output exec {{
         inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
         {
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 0ef2ac6ae..64d000005 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -96,6 +96,11 @@ output decoder {{
 
 }};
 
+output header {{
+    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
+
+}};
+
 output exec {{
     /** return data in cases where there the size of data is only
         known in the packet
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 41f94e129..b4d00454e 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -84,6 +84,17 @@ output decoder {{
     }
 }};
 
+output header {{
+   void getThrRegExValues(%(CPU_exec_context)s *xc,
+                          MipsISA::VPEConf0Reg &vpe_conf0,
+                          MipsISA::TCBindReg &tc_bind_mt,
+                          MipsISA::TCBindReg &tc_bind,
+                          MipsISA::VPEControlReg &vpe_control,
+                          MipsISA::MVPConf0Reg &mvp_conf0);
+
+   void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3);
+}};
+
 output exec {{
     void getThrRegExValues(%(CPU_exec_context)s *xc,
             VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index f8c86a71a..9ce1b8810 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -39,7 +39,8 @@ output header {{
 #include <sstream>
 
 #include "arch/mips/isa_traits.hh"
-#include "arch/mips/types.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 }};
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 148983f4f..1fee832d3 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -276,6 +276,19 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
+void enterREDState(ThreadContext *tc);
+
+void doREDFault(ThreadContext *tc, TrapType tt);
+
+void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
+
+void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
+
+void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
+
+void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
+                   MiscReg TL);
+
 } // namespace SparcISA
 
 #endif // __SPARC_FAULTS_HH__
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh
index 909f8ad79..b51d1bd21 100644
--- a/src/arch/x86/bios/intelmp.hh
+++ b/src/arch/x86/bios/intelmp.hh
@@ -73,6 +73,12 @@ struct X86IntelMPAddrSpaceMappingParams;
 struct X86IntelMPBusHierarchyParams;
 struct X86IntelMPCompatAddrSpaceModParams;
 
+template<class T>
+uint8_t writeOutField(PortProxy& proxy, Addr addr, T val);
+
+uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
+                       int length);
+
 namespace X86ISA
 {
 
diff --git a/src/arch/x86/cpuid.hh b/src/arch/x86/cpuid.hh
index 8d3181819..2414cbeb6 100644
--- a/src/arch/x86/cpuid.hh
+++ b/src/arch/x86/cpuid.hh
@@ -55,6 +55,8 @@ namespace X86ISA
         {}
     };
 
+    uint64_t stringToRegister(const char *str);
+
     bool doCpuid(ThreadContext * tc, uint32_t function,
             uint32_t index, CpuidResult &result);
 } // namespace X86ISA
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 4e6ef4324..de3eea1a6 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -66,8 +66,12 @@
 class ThreadContext;
 class BaseCPU;
 
+int divideFromConf(uint32_t conf);
+
 namespace X86ISA {
 
+ApicRegIndex decodeAddr(Addr paddr);
+
 class Interrupts : public BasicPioDevice, IntDev
 {
   protected: