params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed

6 files changed, 38 insertions, 29 deletions

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 628d7ad6b..2e974effe 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -41,8 +41,6 @@
 #include "base/trace.hh"
 #include "config/alpha_tlaser.hh"
 #include "cpu/thread_context.hh"
-#include "params/AlphaDTB.hh"
-#include "params/AlphaITB.hh"
 
 using namespace std;
 using namespace EV5;
@@ -59,8 +57,8 @@ bool uncacheBit40 = false;
 
 #define MODE2MASK(X)			(1 << (X))
 
-TLB::TLB(const string &name, int s)
-    : SimObject(name), size(s), nlu(0)
+TLB::TLB(const Params *p)
+    : SimObject(p), size(p->size), nlu(0)
 {
     table = new TlbEntry[size];
     memset(table, 0, sizeof(TlbEntry[size]));
@@ -286,8 +284,8 @@ TLB::unserialize(Checkpoint *cp, const string &section)
 //
 //  Alpha ITB
 //
-ITB::ITB(const std::string &name, int size)
-    : TLB(name, size)
+ITB::ITB(const Params *p)
+    : TLB(p)
 {}
 
 
@@ -400,8 +398,8 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 //
 //  Alpha DTB
 //
- DTB::DTB(const std::string &name, int size)
-     : TLB(name, size)
+ DTB::DTB(const Params *p)
+     : TLB(p)
 {}
 
 void
@@ -624,11 +622,11 @@ TLB::index(bool advance)
 AlphaISA::ITB *
 AlphaITBParams::create()
 {
-    return new AlphaISA::ITB(name, size);
+    return new AlphaISA::ITB(this);
 }
 
 AlphaISA::DTB *
 AlphaDTBParams::create()
 {
-    return new AlphaISA::DTB(name, size);
+    return new AlphaISA::DTB(this);
 }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 8df47dbec..69a33f32d 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -41,6 +41,8 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
+#include "params/AlphaDTB.hh"
+#include "params/AlphaITB.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
 
@@ -64,7 +66,8 @@ namespace AlphaISA
         TlbEntry *lookup(Addr vpn, uint8_t asn);
 
       public:
-        TLB(const std::string &name, int size);
+        typedef AlphaTLBParams Params;
+        TLB(const Params *p);
         virtual ~TLB();
 
         int getsize() const { return size; }
@@ -113,7 +116,8 @@ namespace AlphaISA
         mutable Stats::Formula accesses;
 
       public:
-        ITB(const std::string &name, int size);
+        typedef AlphaITBParams Params;
+        ITB(const Params *p);
         virtual void regStats();
 
         Fault translate(RequestPtr &req, ThreadContext *tc);
@@ -136,7 +140,8 @@ namespace AlphaISA
         Stats::Formula accesses;
 
       public:
-        DTB(const std::string &name, int size);
+        typedef AlphaDTBParams Params;
+        DTB(const Params *p);
         virtual void regStats();
 
         Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 41a26aba1..b644ae18d 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -31,8 +31,6 @@
 #include <cstring>
 
 #include "arch/mips/tlb.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
 
 namespace MipsISA {
     Fault
@@ -69,11 +67,11 @@ namespace MipsISA {
 MipsISA::ITB *
 MipsITBParams::create()
 {
-    return new MipsISA::ITB(name);
+    return new MipsISA::ITB(this);
 }
 
 MipsISA::DTB *
 MipsDTBParams::create()
 {
-    return new MipsISA::DTB(name);
+    return new MipsISA::DTB(this);
 }
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 682aa7654..78b4af94d 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -31,6 +31,8 @@
 #ifndef __ARCH_MIPS_TLB_HH__
 #define __ARCH_MIPS_TLB_HH__
 
+#include "params/MipsDTB.hh"
+#include "params/MipsITB.hh"
 #include "sim/tlb.hh"
 
 namespace MipsISA
@@ -48,7 +50,8 @@ namespace MipsISA
     class TLB : public GenericTLB
     {
       public:
-        TLB(const std::string &name) : GenericTLB(name)
+        typedef MipsTLBParams Params;
+        TLB(const Params *p) : GenericTLB(p)
         {}
 
         Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
@@ -57,14 +60,16 @@ namespace MipsISA
     class ITB : public TLB
     {
       public:
-        ITB(const std::string &name) : TLB(name)
+        typedef MipsITBParams Params;
+        ITB(const Params *p) : TLB(p)
         {}
     };
 
     class DTB : public TLB
     {
       public:
-        DTB(const std::string &name) : TLB(name)
+        typedef MipsDTBParams Params;
+        DTB(const Params *p) : TLB(p)
         {}
     };
 };
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index edc9d37a9..093e0356b 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -39,16 +39,14 @@
 #include "cpu/base.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
-#include "params/SparcDTB.hh"
-#include "params/SparcITB.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
  * */
 namespace SparcISA {
 
-TLB::TLB(const std::string &name, int s)
-    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
+TLB::TLB(const Params *p)
+    : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
       cacheValid(false)
 {
     // To make this work you'll have to change the hypervisor and OS
@@ -1437,11 +1435,11 @@ DTB::unserialize(Checkpoint *cp, const std::string &section)
 SparcISA::ITB *
 SparcITBParams::create()
 {
-    return new SparcISA::ITB(name, size);
+    return new SparcISA::ITB(this);
 }
 
 SparcISA::DTB *
 SparcDTBParams::create()
 {
-    return new SparcISA::DTB(name, size);
+    return new SparcISA::DTB(this);
 }
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index d35a6e096..b38ee15dc 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -36,6 +36,8 @@
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
+#include "params/SparcDTB.hh"
+#include "params/SparcITB.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
 
@@ -147,7 +149,8 @@ class TLB : public SimObject
     void writeTagAccess(Addr va, int context);
 
   public:
-    TLB(const std::string &name, int size);
+    typedef SparcTLBParams Params;
+    TLB(const Params *p);
 
     void dumpAll();
 
@@ -163,7 +166,8 @@ class TLB : public SimObject
 class ITB : public TLB
 {
   public:
-    ITB(const std::string &name, int size) : TLB(name, size)
+    typedef SparcITBParams Params;
+    ITB(const Params *p) : TLB(p)
     {
         cacheEntry = NULL;
     }
@@ -182,7 +186,8 @@ class DTB : public TLB
   protected:
     uint64_t sfar;
   public:
-    DTB(const std::string &name, int size) : TLB(name, size)
+    typedef SparcDTBParams Params;
+    DTB(const Params *p) : TLB(p)
     {
         sfar = 0;
         cacheEntry[0] = NULL;