Replace curTick global variable with accessor functions.

This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.

10 files changed, 22 insertions, 22 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index d829ad744..f0aa5a3fd 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -791,7 +791,7 @@ decode OPCODE default Unknown::unknown() {
                 Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
 
 #else
-                Ra = curTick;
+                Ra = curTick();
 #endif
             }}, IsUnverifiable);
 
diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc
index 6e9dc1611..70eeadd8e 100644
--- a/src/arch/alpha/kernel_stats.cc
+++ b/src/arch/alpha/kernel_stats.cc
@@ -143,9 +143,9 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
             Linux::ThreadInfo(tc).curTaskPID());
 
     _modeGood[newmode]++;
-    _modeTicks[themode] += curTick - lastModeTick;
+    _modeTicks[themode] += curTick() - lastModeTick;
 
-    lastModeTick = curTick;
+    lastModeTick = curTick();
     themode = newmode;
 }
 
diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc
index 9aae7e155..b10fea02b 100644
--- a/src/arch/alpha/tru64/process.cc
+++ b/src/arch/alpha/tru64/process.cc
@@ -184,7 +184,7 @@ tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
           TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
 
           const int clk_hz = one_million;
-          elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz));
+          elp->si_user = htog(curTick() / (SimClock::Frequency / clk_hz));
           elp->si_nice = htog(0);
           elp->si_sys = htog(0);
           elp->si_idle = htog(0);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 88f2a455f..6b2113639 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -713,7 +713,7 @@ void
 TableWalker::nextWalk(ThreadContext *tc)
 {
     if (pendingQueue.size())
-        schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick+1));
+        schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1));
 }
 
 
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 1cad7e4be..5cd65cfac 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -528,7 +528,7 @@ ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
+        cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
     }
 }
 
@@ -585,7 +585,7 @@ ISA::CP0Event::description() const
 void
 ISA::CP0Event::scheduleEvent(int delay)
 {
-    cpu->reschedule(this, curTick + cpu->ticks(delay), true);
+    cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
 }
 
 void
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 9d354c46a..1944d69d3 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -201,7 +201,7 @@ def format MT_Control(code, *opt_flags) {{
 
 def format MT_MFTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 
         code += 'if (MT_H == 1) {\n'
         code += 'data = bits(data, top_bit, bottom_bit);\n'
@@ -217,7 +217,7 @@ def format MT_MFTR(code, *flags) {{
 
 def format MT_MTTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
         iop = InstObjParams(name, Name, 'MTOp', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index ddda47a0a..1cc08ee3d 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req)
             if (stCondFailures % 100000 == 0) {
                 warn("%i: context %d: %d consecutive "
                      "store conditional failures\n",
-                     curTick, xc->contextId(), stCondFailures);
+                     curTick(), xc->contextId(), stCondFailures);
             }
 
             if (!lock_flag){
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 3ec6cbe70..c63c65a73 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -81,7 +81,7 @@ haltThread(TC *tc)
         tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
 
         warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
-                curTick, tc->threadId(), tc->getCpuPtr()->name(),
+                curTick(), tc->threadId(), tc->getCpuPtr()->name(),
                 pc.pc(), pc.npc());
     }
 }
@@ -99,7 +99,7 @@ restoreThread(TC *tc)
         tc->activate(0);
 
         warn("%i: Restoring thread %i in %s @ PC %x",
-                curTick, tc->threadId(), tc->getCpuPtr()->name(), restartPC);
+                curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
     }
 }
 
@@ -208,7 +208,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
             tcStatus.a = 0;
             tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
             warn("%i: Deactivating Hardware Thread Context #%i",
-                    curTick, tc->threadId());
+                    curTick(), tc->threadId());
         }
     } else if (src_reg > 0) {
         if (src_reg && !yield_mask != 0) {
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index bd6497b25..efab8b832 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -111,7 +111,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(tick_cmpr & ~mask(63)) && time > 0) {
             if (tickCompare->scheduled())
                 cpu->deschedule(tickCompare);
-            cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
+            cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
         }
         panic("writing to TICK compare register %#X\n", val);
         break;
@@ -127,7 +127,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(stick_cmpr & ~mask(63)) && time > 0) {
             if (sTickCompare->scheduled())
                 cpu->deschedule(sTickCompare);
-            cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
+            cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
         }
         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
         break;
@@ -197,7 +197,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
             if (hSTickCompare->scheduled())
                 cpu->deschedule(hSTickCompare);
-            cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
+            cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
         }
         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
         break;
@@ -335,7 +335,7 @@ ISA::processSTickCompare(ThreadContext *tc)
             setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else {
-        cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
+        cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
     }
 }
 
@@ -363,7 +363,7 @@ ISA::processHSTickCompare(ThreadContext *tc)
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else {
-        cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
+        cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
     }
 }
 
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index cc1d442fe..951392a15 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -394,7 +394,7 @@ X86ISA::Interrupts::readReg(ApicRegIndex reg)
                 uint64_t ticksPerCount = clock *
                     divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
                 // Compute how many m5 ticks are left.
-                uint64_t val = apicTimerEvent.when() - curTick;
+                uint64_t val = apicTimerEvent.when() - curTick();
                 // Turn that into a count.
                 val = (val + ticksPerCount - 1) / ticksPerCount;
                 return val;
@@ -572,13 +572,13 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
             uint64_t newCount = newVal *
                 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
             // Schedule on the edge of the next tick plus the new count.
-            Tick offset = curTick % clock;
+            Tick offset = curTick() % clock;
             if (offset) {
                 reschedule(apicTimerEvent,
-                        curTick + (newCount + 1) * clock - offset, true);
+                        curTick() + (newCount + 1) * clock - offset, true);
             } else {
                 reschedule(apicTimerEvent,
-                        curTick + newCount * clock, true);
+                        curTick() + newCount * clock, true);
             }
         }
         break;