summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:18:29 -0400
committerAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:18:29 -0400
commit71daeb0b2b390f5f5a34addd3993f28851c91d72 (patch)
tree8c6c587dc87fef8deecf3b65b8e931e8a3aa78ee /src/arch
parent8d1e56bdcd673fd3b1ddfd9ac82f7c1ded3110c4 (diff)
downloadgem5-71daeb0b2b390f5f5a34addd3993f28851c91d72.tar.xz
ARM: Fix identification of one RAS pop instruction.
The check should be with the op2 field, not with the op1 field.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/insts/data.isa2
-rw-r--r--src/arch/arm/isa/templates/pred.isa7
2 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 89c0e48c7..97ae7d0c0 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -293,7 +293,7 @@ let {{
buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False,
- isRasPop = "op1 == INTREG_LR", isBranch = "dest == INTREG_PC")
+ isRasPop = "op2 == INTREG_LR", isBranch = "dest == INTREG_PC")
buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
buildDataInst("movt",
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index efb8e470b..88e8fecd1 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -115,11 +115,12 @@ def template DataRegConstructor {{
flags[IsUncondControl] = true;
else
flags[IsCondControl] = true;
- }
- if (%(is_ras_pop)s) {
- flags[IsReturn] = true;
+ if (%(is_ras_pop)s) {
+ flags[IsReturn] = true;
+ }
}
+
}
}};