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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 20:25:06 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 20:25:06 -0700
commit9e1fe2050ac55c28b6601770014193321a4013d0 (patch)
tree6496c5e7c1680da5d53247c4df7232d38126d57d /src/arch
parente9158d763a34d96147d62d08f6ccc4e8ba3308e5 (diff)
downloadgem5-9e1fe2050ac55c28b6601770014193321a4013d0.tar.xz
X86: Let segment manipulation microops be conditional.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/microops/regop.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dfb0abeae..4f93fad80 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -978,7 +978,7 @@ let {{
'''
# Microops for manipulating segmentation registers
- class SegOp(RegOp):
+ class SegOp(CondRegOp):
abstract = True
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(SegOp, self).__init__(dest, \