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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-04-06 19:43:31 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-04-06 19:43:31 +0100
commitbe28d96510e0e722db83b26f1a12d3f5de979b32 (patch)
tree6a7e1807397f002f51fddb34568b89250fca45c8 /src/arch
parent8615b27174ae06db4665016c877b1e88031af203 (diff)
downloadgem5-be28d96510e0e722db83b26f1a12d3f5de979b32.tar.xz
Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.cc5
-rw-r--r--src/arch/arm/vtophys.cc2
2 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d3286a6b0..6f66e5ae1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1521,7 +1521,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
// with unexpected atomic snoop requests.
warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
Request req(0, val, 1, flags, Request::funcMasterId,
- tc->pcState().pc(), tc->contextId());
+ tc->pcState().pc(), tc->contextId(),
+ tc->threadId());
fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
@@ -1767,7 +1768,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
req->setVirt(0, val, 1, flags, Request::funcMasterId,
tc->pcState().pc());
- req->setContext(tc->contextId());
+ req->setThreadContext(tc->contextId(), tc->threadId());
fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
tranType);
diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 24fc5a5c7..3aad35818 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -69,7 +69,7 @@ try_translate(ThreadContext *tc, Addr addr)
Fault fault;
// Set up a functional memory Request to pass to the TLB
// to get it to translate the vaddr to a paddr
- Request req(0, addr, 64, 0x40, -1, 0, 0);
+ Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
ArmISA::TLB *tlb;
// Check the TLBs for a translation