make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered

across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.

4 files changed, 6 insertions, 6 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index f629d982a..6f4f5a748 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -87,7 +87,7 @@ handleLockedWrite(XC *xc, Request *req)
             if (stCondFailures % 100000 == 0) {
                 warn("cpu %d: %d consecutive "
                      "store conditional failures\n",
-                     xc->readCpuId(), stCondFailures);
+                     xc->cpuId(), stCondFailures);
             }
 
             // store conditional failed already, so don't issue it to mem
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 07dc9d588..5877b1439 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req)
             if (stCondFailures % 10 == 0) {
                 warn("%i: cpu %d: %d consecutive "
                      "store conditional failures\n",
-                     curTick, xc->readCpuId(), stCondFailures);
+                     curTick, xc->cpuId(), stCondFailures);
             }
 
             if (stCondFailures == 5000) {
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index e1276b812..6961a24e9 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -257,11 +257,11 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
         temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
         // Check that the CPU array is fully populated
         // (by calling getNumCPus())
-        assert(sys->getNumCPUs() > tc->readCpuId());
+        assert(sys->getNumCPUs() > tc->cpuId());
 
-        temp |= tc->readCpuId()  << STS::shft_id;
+        temp |= tc->cpuId()  << STS::shft_id;
 
-        for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
+        for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
             switch (sys->threadContexts[x]->status()) {
               case ThreadContext::Active:
                 temp |= STS::st_run << (STS::shft_fsm0 -
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 5db678919..17374fa0c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
         */
         // Force the access to be uncacheable.
         req->setFlags(req->getFlags() | UNCACHEABLE);
-        req->setPaddr(x86LocalAPICAddress(tc->readCpuId(), paddr - baseAddr));
+        req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
     }
 #endif
     return NoFault;