ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.

4 files changed, 26 insertions, 33 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index e2947cf4a..937b38fce 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -47,11 +47,6 @@ decode OPCODE default Unknown::unknown() {
         0x23: ldt({{ Fa = Mem.df; }});
         0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
         0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
-#ifdef USE_COPY
-        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
-                                      {{ fault = xc->copySrcTranslate(EA); }},
-                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
-#endif
     }
 
     format LoadOrPrefetch {
@@ -71,11 +66,6 @@ decode OPCODE default Unknown::unknown() {
         0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
         0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
         0x27: stt({{ Mem.df = Fa; }});
-#ifdef USE_COPY
-        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
-                                       {{ fault = xc->copy(EA); }},
-                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
-#endif
     }
 
     format StoreCond {
@@ -788,10 +778,8 @@ decode OPCODE default Unknown::unknown() {
 
         format MiscPrefetch {
             0xf800: wh64({{ EA = Rb & ~ULL(63); }},
-                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
-                         mem_flags = PREFETCH,
-                         inst_flags = [IsMemRef, IsDataPrefetch,
-                                       IsStore, MemWriteOp]);
+                         {{ ; }},
+                         mem_flags = PREFETCH);
         }
 
         format BasicOperate {
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 799f910c3..862fe0878 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -396,6 +396,7 @@ def template MiscExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
+        warn_once("Prefetch instrutions is Alpha do not do anything\n");
         if (fault == NoFault) {
             %(memacc_code)s;
         }
@@ -404,6 +405,8 @@ def template MiscExecute {{
     }
 }};
 
+// Prefetches in Alpha don't actually do anything
+// They just build an effective address and complete
 def template MiscInitiateAcc {{
     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
@@ -530,12 +533,10 @@ def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
     inst_flags = makeList(inst_flags)
 
     pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
-    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
-                                  'IsDataPrefetch', 'MemReadOp']
+    pf_inst_flags = inst_flags
 
     (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
-        LoadStoreBase(name, Name + 'Prefetch', ea_code,
-                      'xc->prefetch(EA, memAccessFlags);',
+        LoadStoreBase(name, Name + 'Prefetch', ea_code, ';',
                       pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
 
     header_output += pf_header_output
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 92ad52a6d..b091da856 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -161,8 +161,13 @@ let {{
             if self.user:
                 self.memFlags.append("ArmISA::TLB::UserMode")
 
-            if self.flavor == "prefetch":
+            self.instFlags = []
+            if self.flavor == "dprefetch":
                 self.memFlags.append("Request::PREFETCH")
+                self.instFlags = ['IsDataPrefetch']
+            elif self.flavor == "iprefetch":
+                self.memFlags.append("Request::PREFETCH")
+                self.instFlags = ['IsInstPrefetch']
             elif self.flavor == "exclusive":
                 self.memFlags.append("Request::LLSC")
             elif self.flavor == "normal":
@@ -185,7 +190,7 @@ let {{
             self.codeBlobs["ea_code"] = eaCode
 
             # Code that actually handles the access
-            if self.flavor == "prefetch":
+            if self.flavor == "dprefetch" or self.flavor == "iprefetch":
                 accCode = 'uint64_t temp = Mem%s; temp = temp;'
             elif self.flavor == "fp":
                 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
@@ -200,7 +205,7 @@ let {{
             wbDecl = None
             if self.writeback:
                 wbDecl = self.wbDecl
-            self.emitHelper(base, wbDecl)
+            self.emitHelper(base, wbDecl, self.instFlags)
 
     def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
         return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
@@ -325,11 +330,11 @@ let {{
         RfeInst(mnem, False, False, True).emit()
         RfeInst(mnem, False, False, False).emit()
 
-    def buildPrefetches(mnem):
-        LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit()
-        LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit()
-        LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit()
-        LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit()
+    def buildPrefetches(mnem, type):
+        LoadReg(mnem, False, False, False, size=1, flavor=type).emit()
+        LoadImm(mnem, False, False, False, size=1, flavor=type).emit()
+        LoadReg(mnem, False, True, False, size=1, flavor=type).emit()
+        LoadImm(mnem, False, True, False, size=1, flavor=type).emit()
 
     buildLoads("ldr")
     buildLoads("ldrt", user=True)
@@ -346,9 +351,9 @@ let {{
 
     buildRfeLoads("rfe")
 
-    buildPrefetches("pld")
-    buildPrefetches("pldw")
-    buildPrefetches("pli")
+    buildPrefetches("pld", "dprefetch")
+    buildPrefetches("pldw", "dprefetch")
+    buildPrefetches("pli", "iprefetch")
 
     LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
     LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index e7dbd8e9b..c4666e4ab 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -452,7 +452,7 @@ def template MiscExecute {{
     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Addr EA;
+        Addr EA M5_VAR_USED = 0;
         Fault fault = NoFault;
 
         %(fp_enable_check)s;
@@ -577,12 +577,11 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 def format Prefetch(ea_code = {{ EA = Rs + disp; }},
                           mem_flags = [], pf_flags = [], inst_flags = []) {{
     pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
-    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
-                                  'IsDataPrefetch', 'MemReadOp']
+    pf_inst_flags = inst_flags
 
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code,
-                      'xc->prefetch(EA, memAccessFlags);',
+                      'warn_once("Prefetching not implemented for MIPS\\n");',
                       pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
 
 }};